An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic

Jason Michael Musicer, M.S. 2000 (advisor: Jan Rabaey)..

The recent development of VLSI technology has allowed rapid growth in the area of portable electronic devices.  Laptop computers, cellular phones, and PDA's have all become commonplace items in people's lives.  One of the primary consumer complaints of these devices is the short battery life and/or the extra weight of the batteries due to the high power consumption of the circuitry.  As CMOS process technology scales and demand for more processing power increases, it can be shown that the power consumption of future IC's will increase over time if significant architectural changes are not made [1].  It is therefore critical in future circuits that power be minimized beyond the traditional constraints of packaging cost and heat dissipation. As device density increases, it is also extremely desirable to integrate analog and digital circuitry onto the same die for many DSP and communications systems.  High levels of integration will be required in order to drive down production costs and reduce total system area.  This integration has been delayed due primarily to the difficulty in designed high precision analog circuitry in the presence of extremely hostile digital switching noise.  These difficulties will also increase as process technology scales due to fundamental challenges in high precision analog design at low supply voltages in digital CMOS technology.  Either significant advances in analog design techniques will be required or digital designers will be forced to adapt their design techniques or process technology.A digital circuit style that seems to be promising in both reducing power consumption and providing an analog friendly environment is MOS Current Mode Logic (MCML).  While bipolar CML, a derivative of emitter coupled logic (ECL) logic, has been used for years in high performance applications, it has become less desirable due to its high static power consumption and reliance on bipolar processing.  In [2], MCML was analyzed and a 64-bit adaptively pipelined adder was developed and simulated.  It was demonstrated in that paper that MCML could dissipate less power than equivalent CMOS circuitry as well as adjust for clock skew and environmental or process variations.In this project, a much broader analysis of MCML is presented with some theoretical development and application to other circuit blocks.  Near-minimum sized transistors are used in this project instead of the significantly larger designs in [2] and power consumption is measured for a wide variety of circuit blocks, performance levels, and design techniques. It will be shown that area efficient MCML can actually consume significantly less power than equivalent CMOS circuitry while maintaining many of the other benefits of traditional CML such as reduction in dI/dt effects, common mode noise immunity, and process and voltage variation immunity.  The most important goal of this project is to evaluate the appropriate domains of performance and power requirements in which MCML presents benefits over current logic styles.