Low-Power Domain-Specific Processors for Digital Signal Processing

Arthur Abnous, P.h.D. 2001 (advisor: Jan M. Rabaey)

Rapid advances in portable computing and communication devices require imple-mentations that must not only be highly energy efficient, but they must also be flexible enough to support a variety of multimedia services and communication capabilities. The required flexibility dictates the use of programmable processors in implementing the increasingly sophisticated digital signal processing algorithms that are widely used in por-table multimedia terminals. However, compared to custom, application-specific solutions, programmable processors often incur significant penalties in energy efficiency and perfor-mance. The approach taken in this work was to explore ways of trading off flexibility for increased efficiency. This approach was based on the observation that for a given domain of signal processing algorithms, the underlying computational kernels that account for a large fraction of execution time and energy are very similar. By executing the dominant kernels of a given domain of algorithms on dedicated, optimized processing elements that can execute those kernels with a minimum of energy overhead, significant energy savings can potentially be achieved. Thus, the approach taken in this work yields processors that are domain-specific. The main contribution of this work is a reusable architecture tem-plate, named Pleiades, that can be used to implement domain-specific, programmable pro-cessors for digital signal processing algorithms. The Pleiades architecture template relies on a heterogeneous network of processing elements, optimized for a given domain of algorithms, that can be reconfigured at run time to execute the dominant kernels of the given domain. To verify the effectiveness of the Pleiades architecture, prototype proces-sors were designed, fabricated, and evaluated. Measured results and benchmark studies demonstrate the effectiveness of the Pleiades architecture.