SF2VHD: A Stateflow to VHDL Translator

Kevin Camera, M.S. 2001 (advisor Prof. Brodersen.

Purely HDL and synthesis-based design flows have been characterized by iterative design processes with no guaranteed bound on the time requirement from concept to product. A new methodology for the design of digital communication components has evolved at the Berkeley Wireless Research Center which utilizes techniques in module characterization, clock tree generation, performance estimation, and layout generation to quickly design dedicated hardware in a single pass. As part of this effort, a unique methodology was derived for converting high-level control definitions into hardware. This functionality is now provided by the focus of this work: SF2VHD, a tool which translates state machines in the Stateflow graphical language into VHDL capable of synthesis into hardware. 

Stateflow is a very rich graphical and textual language based closely on the original StateCharts language defined by Harel. It uses a purely software-based execution model and provides sophisticated features like state hierarchy, parallel processes, event triggers, and multi-decision transition conditions. Such a complex language clearly does not map natively into hardware, and it is the role of SF2VHD to find suitable hardware implementations for Stateflow language constructs and achieve an acceptable level of area and power efficiency. While the vast majority of Stateflow features are supported by SF2VHD, several non-essential features were left out for the sake of preserving hardware and simplifying the implementation of the tool. 

SF2VHD itself is written in a hybrid of C and C++, and works by first parsing in the text file containing the Stateflow description into an internal object model, followed by generation of VHDL code for an equivalent state machine. The internal object model closely resembles the raw functionality of the state machine, and theoretically could be used to drive other target file formats. The generation of VHDL code is composed primarily of two processes. First, Stateflow data types are converted to bit-accurate VHDL data types, both at declaration and “automatically” within every expression operation. Second, the Stateflow expression syntax and operators are converted to their VHDL equivalents on a line-by-line basis to   implement the functional behavior of the state machine. Functional equivalence to the software model of Stateflow is also provided by an extended synchronous reset and persistent output latches to preserve values across clock cycles. These features are added intrinsically by SF2VHD. 

The VHDL code generated by SF2VHD achieves a satisfying level of efficiency in hardware after synthesis. Many test cases were used to prove the concepts proposed in this project, which are composed of two separate wireless receiver designs and a pair of contrived examples to fill in features not tested by the other state machines. The metrics for all these hardware designs, along with the methodologies used to cross-verify the hardware implementations, are presented at the end of this work.