High Throughput Low-Density Parity-Check Decoder Architectures

E. Yeo, P. Pakzad, B. Nikolic, V. Anantharam,
 Proceedings IEEE Global Conference on Communications, Globecom’01, San Antonio, TX,
November 25-29, 2001, pp. 3019-3024.

Two decoding schedules and the corresponding serialized architectures for low-density parity-check (LDPC) decoders are presented. They are applied to codes with parity-check matrices generated either randomly or using geometric properties of elements in Galois fields. Both decoding schedules have low computational requirements. The original concurrent decoding schedule has a large storage requirement that is dependent on the total number of edges in the underlying bipartite graph, while a new, staggered decoding schedule which uses an approximation of the belief propagation, has a reduced memory requirement that is dependent only on the number of bits in the block. The performance of these decoding schedules is evaluated through simulations on a magnetic recording channel.