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Limitations and Challenges of
Computer-Aided Design
Technology for CMOS VLSI
Randal E. Bryant, Kwang-Ting
Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly,
Richard Newton, Lawrence Pileggi, Jan M. Rabaey, and Alberto
Sangiovanni-Vincentelli
As manufacturing technology
moves toward fundamental limits of silicon CMOS processing, the ability to
reap the full potential of available transistors and interconnect is
increasingly important. Design technology (DT) is concerned with the
automated or semiautomated
conception, synthesis, verification, and eventual testing of
microelectronic systems. While manufacturing technology faces fundamental
limits inherent in physical laws or material properties, design technology
faces fundamental limitations inherent in the computational intractability
of design optimizations and in the broad and unknown range of potential
applications within various design processes. In this paper we explore
limitations to how design technology can enable the implementation of
single-chip microelectronic systems that take full advantage of
manufacturing technology with respect to such criteria as layout density,
performance, and power dissipation. One limitation is that the integrated
circuit (IC) design process—like any other design process—involves
practical tradeoffs among multiple objectives. For example, there is a
need to design correct and testable chips in a very short time frame and
for these chips to meet a competitive requirement. A second limitation is
that the effectiveness of the design process is determined by its context—the
design methodologies and flows we employ, and the designs that we essay—perhaps
more than by its component tools and algorithms. If the methodology
constrains the design in a particular way (e.g., row-based layout, or
clocked-synchronous timing), then even if individual tools all perform “optimally,”
it may be impossible to achieve an optimal result. On the other hand,
without methodological constraints there are too many degrees of freedom
for developers of design technology to adequately support the designer. A
third limitation is that while the design process as a whole seeks to
optimize, the underlying optimizations are computationally intractable.
Hence, heuristic approaches with few if any guarantees of solution quality
must be ever-present within design technology. This is perhaps the sole
“fundamental limit” in design technology. Design technology by itself
does not impose any fundamental limits on what can be implemented in
silicon. And while “optimal use of silicon technology” is an ill-posed
objective (going far beyond the scope of algorithms, tools, methodologies,
and infrastructure), design technology is the key to approaching and
realizing the limits imposed by other aspects of the design process. In
this paper, we summarize the mainstream methodologies used by CMOS silicon
designers today and—against the backdrop of International Technology
Roadmap for Semiconductors (ITRS) forecasts—point out basic limitations
in their ability to achieve “optimal” design quality using reasonable
resources. In each area of today’s mainstream design flow, we either
identify and quantify the factors limiting progress or point out the work
that must be done to obtain such an understanding. In particular, we
emphasize the role of metrics in the design process and how we might
establish them. Finally, we present a number of potential solutions to
these problems in the form of methodological approaches and major
outstanding research questions that are being considered actively within
the design technology research community. |
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