Architectures and Implementations of Low-Density Parity Check Decoding Algorithms

E. Yeo, B. Nikolic, and V. Anantharam
invited paper at IEEE International Midwest Symposium on Circuits and Systems, Aug 4-7, 2002.

Architectures for low-density parity-check (LDPC) decoders are discussed, with methods to reduce their complexity. Serial implementations similar to traditional microprocessor datapaths are compared against implementations with multiple processing elements that exploit the inherent parallelism in the decoding algorithm. Several classes of LDPC codes, such as those based on irregular random graphs and geometric properties of finite fields are evaluated in terms of their suitability for VLSI implementation and performance as measured by bit-error rate. Efficient realizations of low-density parity check decoders under area, power, and throughput constraints are of particular interest in the design of communications receivers.