A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems

W. R. Davis, N. Zhang, K. Camera, D. Markovic, T. Smilkstein, M. J. Ammer, E. Yeo, S. Augsburger, B. Nikolic, R. W. Brodersen,
IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 420-431, March 2002.

A hierarchical automated design flow for low-energy direct-mapped signal processing integrated circuits is presented. A modular framework based on a combined dataflow graph and floorplan description drives automatic layout generation with com-mercial CAD tools. Automatic characterization of layout improves system-level estimates. Simplified physical design methodologies for low supply voltages are discussed. The flow is demonstrated on a 300-k transistor test-chip, a time-division multiple-access base-band receiver, and a soft-output Viterbi decoder. An example of architectural comparison of energy efficiency is presented.