Energy-Delay Tradeoffs in Combinational Logic using Gate Sizing and Supply Voltage Optimization

V. Stojanovic, D. Markovic, B. Nikolic, M.A. Horowitz, R.W. Brodersen
Proceedings of the 28^th European Solid-State Circuits Conference, ESSCIRC'2002, Florence, Italy, Sept. 24-26, 2002. pp. 211-214.

This paper relates the potential energy savings to the energy profile of a circuit. These savings are obtained by using gate sizing and supply voltage optimization to minimize energy consumption subject to a delay constraint. The sensitivity of energy to delay is derived from a linear delay model extended to multiple supplies.
The optimizations are applied to a range of examples that span typical circuit topologies including inverter chains, SRAM decoders and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that achieving peak performance is expensive in terms of energy.