Implementation of High Throughput Soft Output Viterbi Decoders

E. Yeo, S. Augsburger, W. R. Davis, and B. Nikolic'
Proceedings of IEEE Workshop on Signal Processing Systems, pp. 146-151, San Diego, CA, Oct. 16-18, 2002.

The architectural considerations for VLSI implementations of soft output Viterbi decoders are presented. Structural transformation of the add-compare select structures provides high throughput with small area overhead. Modifications to the survivor memory unit and a comparison between the register exchange and memory traceback methods are highlighted. A 4mm2 demonstration chip, consisting of two parallel, 8-state, 7- bit soft output Viterbi decoders, has been implemented in 0.18µm CMOS technology, and decodes at 500Mb/s with 1.8V supply. These decoders are used with Turbo codes, which have been demonstrated to achieve information rates close to the Shannon limit.