Using Dual-Supply, Dual-Threshold and Transistor Sizing to Reduce

Power in Digital Integrated Circuits

Stephanie Ann Augsburger, 2002 M.S. (advisor: Borivoje Nikolic)

In both high and low performance circuits, both active and leakage control of power consumption is critical. This research focuses on the use of multiple threshold voltages, multiple supply voltages and transistor sizing to reduce power in digital circuits. Non-critical paths are slowed down by either raising the threshold voltage, lowering the supply, downsizing gates, or a combination of these techniques.  A framework, based on gate models extrapolated from circuit-level simulation, was developed in order to evaluate these techniques. Using the framework, the effects of dual-supply (with two different values for the low supply voltage), dual-threshold and sizing were considered on a general logic block in order to gain a consistent idea of how and when these techniques should be used. In total, fifteen different techniques or combination of techniques were applied to the baseline design with varying results This research shows promising results. Energy savings from these three base techniques can be compounded through proper combination for additional benefit. The order of application of these techniques determines the final savings in active and leakage power. Lowering supply, downsizing gates, and then raising transistor threshold, in order of effectiveness, are the keys to controlling active power. Multiple-threshold design is the most effective for leakage power control. It is believed that these results will motivate additional CAD support for designs employing a combination of power reduction methods.