Massively Parallel Wireless Reconfigurable Processor Architecture and Programming

Konstantinos Sarrigeorgidis, Jan M. Rabaey
 10th Reconfigurable Architectures Workshop RAW 2003,  April 22, 2003, Nice, France.

We propose a massively parallel reconfigurable processor architecture targeted for the implementation of advanced wireless communication algorithms that feature matrix computations. A design methodology for programming and configuring the processor architecture is developed. The design entry point is the space representation of the algorithm in Simulink. The Simulink description is parsed and the algorithm's Dependence Flow Graph is derived, which is scheduled and space-time mapped onto the proposed architecture. The compiler reconfigures the switch boxes of the proposed hierarchical interconnection network in the architecture. An energy consumption model is derived, and design examples are provided that demonstrate the enhanced energy efficiency of the proposed architecture compared to a state of the art programmable DSP.