High-Performance Pipeline A/D Converter Design in Deep-Submicron CMOS

 Yun Chiu, 2004 Ph.D. Thesis

Advisor: Paul Gray

Abstract:

Analog-to-digital converters (ADCs) are key design blocks in modern microelectronic digital communication systems. With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage ADCs that can be realized in a mainstream deep-submicron CMOS technology.

Intended for embedded communication applications, specifications of these converters emphasize high dynamic range and low spurious spectral performance. For example, the worst-case blocking specs of some wireless standards, such as GSM, dictate a conversion linearity of 14-16 bits to avoid losing a weak received signal due to distortion artifacts. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons.

Another hurdle to achieve full system integration stems from the power efficiency of the A/D interface circuits supplied by a low voltage dictated by the gate-oxide reliability of the deeply scaled digital CMOS devices. It has been observed recently that these interface analog/mixed-signal circuits are gobbling a larger chunk of the chip area as well as total power consumption; hence it becomes essential to accomplish an optimized design from both the architecture and the circuit standpoints. To achieve high linearity, high dynamic range, and high sampling speed simultaneously under low supply voltages in deepsubmicron CMOS technology with low power consumption has thus far been conceived of as extremely challenging.

This thesis addresses these challenges using the pipeline ADC as a demonstration platform. Specific new design techniques/algorithms include (1) a power-efficient, capacitor ratio-independent conversion scheme, (2) a pipeline stage-scaling algorithm, (3) a nested CMOS gain-boosting technique, (4) a .Σ common-mode voltage regulation circuit, (5) an amplifier and comparator sharing technique, and the use of minimum channel-length, thin oxide transistors with clock bootstrapping and in-line switch techniques. The prototype design of a 14-3 bit pipeline ADC fabricated in a 0.18- µm CMOS technology that achieves an over 100-dB spurious-free dynamic range (SFDR) demonstrates the effectiveness of these techniques.