An Automated Analog Layout Generation Flow

Patrick T. McElwee, 2005 MS Thesis

Abstract:

Modern day IC’s attempt to provide system on chip (SOC) functionality, which requires the co-development of both analog and digital blocks and the integration of these blocks to create a system. The plethora of CAD tools ava ilable to designers of digital blocks for these SOC’s allows the designer to push a digital design in to the layout phase at a much faster rate than analog blocks. Thus, this push for higher levels of integration on chip places pressure on analog designers to reduce the development time of their analog circuits.

Possibly the most tedious and time-consuming aspect of analog circuit design is the layout phase. Traditionally, each polygon had to be drawn by hand in order to realize layout. Now, complete devices or even complete blocks can be drawn using parameterized cells. However, as far as mainstream industrial use is concerned, this is as far as analog layout automation has progressed. Tools such as BALLISTIC, ILAC, KOAN/ANAGRAM, and others have been developed in the university setting but have not caught on in industry. Thus, analog layout still remains a time- intensive task.

The most recent and most industrial focused analog layout tool to come to market is NeoLinear’s NeoCell. NeoCell allows the designer to place layout constraints on devices, placement and nets in order to generate layout from a schematic. The goal of this research is to develop an analog layout tool that uses commercial CAD tools, NeoCell, Virtuoso Custom Router (VCR), and Cadence’s SKILL language, to create layout from a device schematic with as little user interaction as possible. The end goal being a solution that is more catered toward broad industrial use.

The structure of this thesis will be to describe the fundamentals of analog layout and why  it is more difficult than digital layout. Several of the university developed analog layout tools will then be introduced, followed by this research. Finally, examples of how to generate layout using this tool, and the performance of the resulting circuits will be given.