Main Functions:

• GUI Matlab program that drives the Xilinx ISE backend tools to synthesize the VHDL design netlist generated from Xilinx System Generator (XSG), then place and route the design for the given FPGA chip, and generates the bit stream file.
• Other functions include running VHDL simulation at various stages of the above process using ModelSim.
• BEE ISE also selectively run BEE Post XSG processes on the outputs from XSG, before running the Xilinx backend tools.

How to run it:

1. Make sure \\hitz\designs\BEE\mlib is included your Matlab path variable.
2. From Matlab command console, type "bee_ise" to bring up the GUI as shown above.
3. Either type in the Simulink design name, or use the GCS button to select the current design, then choose the correct Xilinx System Generator version number. Currently V2.1 and V2.2 are supported.
4. Choose the correct FPGA part, when the chip string is clicked on, a default value for the CLK pin will show up in the CLK pin field. When compiling design for BEE system, the chip choice should be "XCV2000E-6-FG680". The default choice of the CLK pad is "BUFGP". This field should not be changed, unless necessary.
5. Choose the Synthesis options. The "speed" and "area" options use Xilinx XST as synthesizer, while "Synplify Pro" option uses Synplicity Synplify Pro as synthesizer. The "incremental synthesis" check box is provided for advanced user only, and only works with XST. Typically, by choosing Synplify Pro as the synthesizer eliminates the need to incremental synthesis.
6. Choose the Implementation Options. This option changes the algorithm used by the Xilinx Place & Route tool. "Fast Runtime" provides the fastest runtime compilation, and typically provides decent result. "High Effort" takes more time to place and route, sometimes provide better result. "Balanced" tries to strike a balance between the compilation time and the P&R result. When the "Assign I/O Pads" boxed is checked, BEE_ISE will check the I/O assignment from the Simulink design during implementation stage, and uses the most up to date I/O pads. The option is useful when the same Simulink design is used to either different chips with different I/O assignment, such that the user do not need to rerun XSG to get the I/O assignment.
7. Choose the configuration options. Unless using "JTAG" chain programming, the configuration should use "SelectMap" option.
8. Choose the design flow step(s), then click on the "Run ISE" button to run the flow.
9. If desire to view logs/reports, select the log/report of interest and then click on the "View Report" button.

Design Flow Steps Supported:

• Complete Build: automatically run the synthesis, implementation, and configuration steps. This generates the bit file. For most design, this step is the most commonly used.
• Pre ChipScope: run the synthesis and translate step. Then Xilinx ChipScope Core Inserter should be run to insert the ILA/ICON cores in to the user design. If XST is used as synthesis, the input netlist to ChipScope whould be "design_name.ngc"; if Synplify Pro is used, the netlist should be "deisgn_name.edf". After the ChipScope Core Insertion, Post ChipScope step should be run to generate the bit file. This step is equivalent to running Synthesis then Translate step.
• Post ChipScope: takes the output from Xilinx ChipScope Core Inserter, implement and configures to generate the bit file. This step is equivalent to run implementation then configuration step.
• Synthesis Only: synthesize the design to either NGC (XST)  or EDIF file (Synplify Pro).
• Translate Only: translates the netlist from the synthesizer, required before ChipScope core insertion.
• Implementation Only: translates, maps, place & route the design output from synthesizer. Generates complete NCD file.
• Configure Only: configures the NCD file output from the implementation step into bit file.
• Behavioral VHDL Simulation: takes the VHDL generated from XSG directly and simulate using ModelSim.
• Post Translate VHDL Simulation: requires synthesis and translate step. Simulates the structure VHDL in ModelSim.
• Post PAR VHDL Simulation: requires synthesis and implementation step. Simulates the structure VHDL in ModelSim, along with all VITAL timing modeling of the FPGA primitive components and the nets.

Viewable Log/Report Files:

• When BEE ISE is running, the log of the process is printed on the Matlab command console as well as saved into the XFLOW log, except when using Synplify Pro for synthesis, during which the log is only save into the Synplify log file, not displayed on the Matlab console.
• XFLOW log: logs all Xilinx backend tools progress and output.
• Synplify Log: logs Synplify Pro progress and output.
• MAP report: post MAP report of the FPGA area resource utilization.
• Timing Report: post PAR timing report.
• UCF File: User constraint file, used in translate step. For advanced user, this file can be changed to fine tune a design.

Commonly Encountered Errors:

• When the design flow completes successfully, a dialog box will popup reporting the completion and the total time it took. If any error were encountered during the design flow, the dialog box will report any error.
• All BEE ISE design flow related errors are reported in the XFLOW log, and on the Matlab console, except errors from Synplify Pro synthesis step, which are reported in the Synplify Pro log.
• During translate step, the NGDBuild program sometimes report "INST *** Not found", this is due to the optimization done in the synthesis step, which removes/shares resource. This is not any error of the design or the design flow. The solution is to remove the corresponding "INST" line from the UCF file.