BEE Partition


Step 1: partition the design by grouping into different subsystems. Each subsystem will be implemented on one FPGA. Xilinx Gateways are needed in each subsystem to define the boundary of the FPGA pins. Each subsystem should also have a Xilinx System Generator block defined.
	Step2: tag each subsystem block with the name of the FPGA/XBAR on the BEE board. Refer to the BEE board coordinate system for valid naming conventions.

	Step3: if external connections are needed, tag the corresponding Xilinx Gateway block with the desired external connector name. Refer to BEE board external connection documentation for valid naming conventions. The format's connXX_busX Special tag values: led: single user LED pin, active high rst: single global reset pin, active high


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