FIFO and Dual Port RAM are not currently supported by the ASIC flow. DDS, CIC, FFT are not currently supported by the ASIC flow All communication components are not supported by the ASIC flow Convolutional Encoder, Puncture, Depuncture are available for FPGA usage, while the rest components are not. All four components are not supported by the ASIC flow, but are available for FPGA flow. For better way of controller design, please use StateFlow and SF2VHD The three gateways are supported by both ASIC and FPGA flow, while the rest are only for simulation purpose.

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