Text Box: Digital Circuits Design Group

Text Box: Berkeley Wireless Research Center, EECS, U.C. Berkeley

Text Box: DCDG

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Text Box: Digitally Calibrated Pipeline ADC Designer: Bill Tsang Date: July 2007 Description: This project investigates the possibilities of enhancing ADC performance using digital signal processing techniques. It uses a slow-but-accurate sigma-delta ADC as a reference to correct the error from a high-speed pipelined ADC. The analog circuits including the sigma-delta and the pipelined ADCs have been implemented in 0.13um standard digital CMOS process while the DSP is implemented in a FPGA.

Text Box: 45nm Test Chip for Variability Investigation Designers: Zheng Guo, Liang-Teck Pang, Andrew Carlson, Kenneth Duong Date: Taped out Jun 2007 Description: Test chip to measure variability in SRAM cells in large SRAM arrays, and the impact of layout on CMOS logic in 45nm technology. Contains padded out SRAM cells in small arrays, large SRAM arrays with analog multiplexors on the bitlines, and a large ring-oscillator and leakage transistor array.

Text Box: 2-1 MASH SD ADC Designer: Bill Tsang Date: June 2005 Description: A 1.2 V sigma-delta modulator achieves 97 dB peak SFDR and 82 dB peak SNDR at 1 MS/s was fabricated in 0.13 um standard digital CMOS process. Using high-gain op-amps and bootstrapped sampling switches allow us to obtain 97 dB SFDR. The 2-1 MASH architecture provides a third-order noise-shaping to achieve 82 dB SNR. It dissipates only 11 mW while running at 64 MHz clock frequency.

Text Box: 64-bit Ling Adder Designers: Sean Kao, Radu Zlatanovici, Valentin Abramzon, Elad Alon Date: Taped out Jan 2005, tested May - June, 2005 Description: 8 64-bit domino adder cores

Text Box: 90nm Test Chip for Variability Investigation Designer: Liang-Teck Pang Date: Dec 2004 Description: Die photo of the 90nm testchip used to investigate the effects of layout on cmos performance. This chip contains an array of ring oscillators and off-transistors. Measurement of the ring oscillator frequencies and the off-transistor leakage currents are collected and analysed to obtain variation and spatial correlation statistics.

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( Last modified: Jan 11, 2008)