SSHAFT Macro Design Tutorial

last modified 10/17/00

This brief tutorial describes the steps needed to create and test a SSHAFT ICMacro using Module Compiler.  The files relevant to this tutorial can be found in /tools/sshaft/design/macrotut.

  1. Set up your environment to use Exceed, copy the dot-files to your home directory, and source the setup-script as described in the SSHAFT Setup page.
  2. Create a directory in which you will run the flow.  The ICMake tools which implement much of the design flow assume that this directory contains a certain tree-structure which will be described during this tutorial.  In general, you will see two directories in the root directory:
  3. cd to the directory you just created.
  4. Create a library with the following command:
            createLib.pl mylib
    Note that the subdirectory run/cds was created for running Cadence Design Framework II tools, and the data/dfII/mylib directory was created to collect the data files.  This command can take multiple library names as arguments.
  5. cd to run/cds.
  6. Start the Cadence Design Framework II by typing "icfb &"
  7. We will now create a counter macro using Module Compiler.  First, create a cell called countmc in the mylib library.  As a convention, you can set the view name to "raw" and open with Virtuoso, but any view name and type will do.  This cell will contain the design data generated in this tutorial.
  8. Copy the file count.mcl to the root of your design flow directory-tree.
  9. Open the mylib countmc raw cell for editing and click somewhere inside the window to make it your "current edit cell view".
  10. Hit Shift-Q to edit the cell-view properties.  Add a string property called "bjcView_Scan" and set the value to "1" (don't include the quotes in the string value).  This will cause the scan-chain to be inserted when the macro is elaborated.  Omit this property to omit the scan chain.
  11. Enter the following command in the CIW:
            bjcMCSynth( "../../count.mcl" "COUNT" ?clk "CLK" )
    This will launch Module Compiler to synthesize the counter, launch Design Compiler to insert the scan chain, and import the edif file into a view named "elaborated".  Note that the run/mc and run/dc directores are created for this purpose.  You can invoke these tools from their respective run-directories manually, if you wish.  The options for bjcMCSynth are as follows:
  12. Note that the following files have been created in the directory data/other/mylib/countmc:
  13. Note also that a new view called "elaborated" has been created for mylib countmc.  Close the "raw" view and open the "elaborated" view.
  14. Type the following commands:
            listinst
            listterm
            listnet
    These commands simply list the instances, terminals, and nets of the currently opened cell view.  They can be helpful when debugging to see if your macro was synthesized correctly.
  15. Enter the following command in the CIW:
            bjcStitch
    This command is generally used for stitching the raw and elaborated views together into a format more easily used by the flow.  In this case, it simply produces a new view called "stitched".
  16. Exit icfb and cd back to the root of your design flow directory tree.
  17. Enter the following command:
            epicSim.pl -src mylib countmc stitched -clk CLK
    This command generated an hspice netlist for the cell you just created and puts it in the file data/other/mylib/countmc/netlist.sp.  It also copies the netlist into the run/epic directory and filters it for use with epic (eliminates diodes, etc.).  Lastly, it invokes the m2epic_vec.pl script to create EPIC run decks and convert Simulink test-vectors to EPIC test-vectors.  Other possible arguments to epicSim.pl include

Routing the Macro

  1. cd back to the run/cds directory and run icfb again.
  2. Type the following commands, one after the other.  This advances the design flow through the logic_ctgen, skel_ctgen, and skel_fpgen steps.
  3. Exit icfb and go back to the root of your design flow directory tree.
  4. Enter the following command:
            skelFPGen.pl -lib mylib -cell countmc
    This will generate the autoLayout hierarchy and convert the view to the Pillar database
  5. cd to the run/dp directory and run Design Planner with the command areaPdp &
  6. Open the the autoLayout view of cell countmc in library mylib.
  7. Type the follwing commands in the Design Planner command window:
            (listinst)
            (listterm)
            (listnet)
    These commands are identical to their SKILL equivalents.  Note however, that supply and ground nets and terminals (vdd! and gnd!) have been added to the view.
  8. Type the following command in the Design Planner command window:
            (bjcDrawRows ?density 0.9 ?aspect 4.0)
    This draws standard cell rows with a target row utilization of 90% and an aspect ratio of 4.0.  The procedure will attempt to draw rows which meet your specifications as closely as possible.  Check the log window for the resuling density and aspect ratio.
  9. Position the cursor in the edit window and hit the "B" key.  This will compact the PRBoundary shape around the rows you have just drawn.
  10. Type the following command in the Design Planner command window:
            (bjcQP ?pinopt t)
    This invokes the QPlace placement tool and instructs it to optimize the pin positions while it places cells.
  11. Design Planner will print many messages to the log window and eventually  return unsuccessfully.  If you scroll up in the window, you will eventually find a message like the following:
            The site utilization is = 279.3 is too high!
            *ERROR* Impossible to place without overlaps!
    This error occurs because the floorplan is too dense.  The bjcDrawRows function takes into account cell area but not pin area when determining density.  The ratio of pin area to total area is related to the ratio of perimeter to area, so this ratio is higher for smaller cells.  While 90% densities are reasonable for large cells, we should probably use 50% or lower for a cell this size.
  12. Choose BWRC -> FP Init.  This will re-initialize the cell-view and erase the rows you just drew.  This command also closes the cell-view, so you will have to re-open it.
  13. Draw rows with a density of 0.4 and compact the PR Boundary as in steps 7 and 8.
  14. Run QPlace again as in step 9.  The Cells should be placed successfully.
  15.  Choose BWRC -> FP Save to save your floorplan.
  16. Exit Design Planner and go back to the root of your design flow directory tree.
  17. Type the following command:
            routeSingle.pl -lib mylib -cell countmc
    This will add filler cells to your design, invoke IC Craftsman to route, and convert the result to a DFII layout view.
    NOTE:  If IC Craftsman runs unsuccessfully for any reason, you will see the following error message in the areaPdp.log file:
            ERROR -*- Invalid Command, sh -c "'cd ../icc ; ic_craft.exec'"
    One common problem is that the DISPLAY environment variable is set at login time with the parenthost command.  Since routeSingle.pl invokes IC Craftsman through a remote procedure call, the DISPLAY variable will be set incorrectly, causing IC Craftsman to crash.  To circumvent this problem, either remove the DISPLAY settings from your .cshrc or .login file or invoke routeSingle.pl with the -nogr option to turn off graphics while routing.
  18. Type the following command:
            verifyLayout.pl -lib mylib -cell countmc
    This invokes Calibre DRC and LVS on the cell you just routed.  You should see the following log messages:
            DRC Completed with 96 error(s)
            LVS Reports that the netlists match
    The first message is bad news, but the second is pretty good. Since the cell passes LVS, however, we can proceed with parasitic extraction in Arcadia.
  19. Type the following command:
            extractLayout -lib mylib -cell countmc
    This invokes Arcadia extraction and produces a flat netlist called extracted.sp in the directory data/other/mylib/countmc.  
  20. Coming soon... EPIC simulations with the extracted netlist...

maintained by Rhett Davis
wrdavis@eecs.berkeley.edu