Using ICMAKE with stateflow
This tutorial assumes that you already have knowledge of Rhett's
icmake tutorial and icmake
help page.
It also assumes that you have looked at Kevin's
StateFlow 2 VHD help page.
What I have here is a finished design that I will step through and explain
how it is different then Rhett's 'mychip' example.
The Files referenced here are located in
\\hitz\Users\bcoates\matlab\sf2\ in this directory there is a
folder for each Stateflow machine in Paul's SCR1 design and other sub designs of
the chip. The only ones that have been modified to work with the flow are PLL_Control
and Pilot_Ack_Control. due to changes in bcc.
In the sf2 directory there is the library 'flow' that contains these two
blocks.
Each state flow folder contains another folder named vectors, these are the test
vectors that were produced with simulink and will be used to test the results.
My icmake run directories and located in the unix home ~bcoates/ICFlow/sf2/ - there are sub dir for each chart.
First set up your environment like Rhett says.
Then make a new library - this will be the top level of you design. equivalent
to 'mychip' you can go ahead a use the mychip from the fundamental library. I
just called mine test and put it in the library called test. These don't have to
be the same name, but I think Rhett wants them to be.
SO if you open the file called 'test' in the \\hitz\users\bcoates\matlab\sf2\PLL_Control dir you will see:
You see that this is a ICDesign and it has seven inputs and
they don't have real names like ScanIn etc.
What I did was cheat and Ill tell you why:
If you look under this mask you will see there is a ICMacro named PLL_Control,
this is the only block I am interested in making. In the Hspicenetlist step I
choose to only get the netlist of the PLL_Control block and not the top level
block (the whole design)
This shows that in a big design you can choose to pull a piece of hierarchy out
of the design and ignore the rest.
So that is why I ignored the names and output wires.
However the flow requires that you have a ICDesign as your top level and also it
needs to know the data types of the inputs to PLL_Control to build it. That is
why I only have the inputs data types specified but I don't care about their
names.
I also don't have the T parameter in the mask set to 40e-9, I
left this out because I never simulated this in simulink
but you should put it in.
So this thing above is the subsystem in the the block called
'test' that is in the library called 'test'
We can see the seven input that I didn't care about their names. If you click on
PLL_Control to look at its mask you will see below:
First of all I want to say PLL_Control is actually a link from a different
library called flow. This library should contain all your stateflow blocks to be
used in the design. The PLL_Control you see above as a subsystem to test was
dragged from this library flow.
If you look under PLL_Control you will see what is below:
Strange things with the scan lines and the reset. This is okay. They need to be
there for the netlister, although they serve no purpose in simulink. The rounded
block is the actual stateflow chart which if you click on it it will open as
below with the brown background.
So when you build this thing you have to build it like that or it doesn't
work.
Important Stuff:
Look at Simulink
design flow Parameter reference - brings you to the Elaboration type
section.
We see that we can use either VHDL or StateFlow.
Also look at Rhett' tut to see how to edit the mask.
Every ICMacro must have a elaboration type:
bjcView_ElaborationType - for any kind of StateFlow must
be either VHDL or StateFlow
In my example mask I used VHDL- this means that I have used Kevin's script to
make a VHDL file before I ran the flow and when the flow is run it uses the vhdl
code as its source and ignores the actual chart.
Required Parameters for VHDL are:
bjcView_SourceFile - this is the path and name of your
vhdl file (you can see from the mask I used where the vhdl file is- btw - its
still there if you want to look)
bjcView_EntityName - this is the name of your VHDL Entity which is
required because this could be different then the name of vhdl file (this name
is the name of the rounded block in simulink- I think) - hint: just name
everthing the same name to avoid mistakes.
If you want the flow to do it all for you use Parameter for
StateFlow,
Required Parameters for Stateflow are:
bjcView_StateflowChart - this is the name of the round
simulink block
bjcView_StateflowMDLFile - the name of MDL file which contains the chart
( I'm not sure if this is the top level or the flow library)
There is one other Parameter that must be there also to make a total
of four 'special' parameters this is for the clock name:
bjcAddClk - this should be filled with BCLK the name of the clock net of the design.
So what ever way you want to do it. If you want to write vhdl by hand and use it in the flow use the VHDL type. If you have total faith in kevin's translator and the flow use StateFlow type.
This is the PLL_Control chart.
ICMakefile:
--------------------------------------------------------------------------------------------------------------------------
DESIGN = test
SOURCEFILE = test.mdl
LIBFILES = fundamental.mdl route.mdl flow.mdl test.mdl
MDLPATH = /vol/hitz/vol1/designs/scr/scr_shadow/receiver/digital/precompiled /vol/hitz/hitz/users/bcoates/matlab/sf2/PLL_Control/
/vol/hitz/hitz/users/bcoates/matlab/sf2/
TOLERANCE = high
all: bcc elab ein buf sim
sim:
EPIC = PLL_Control flow PLL_Control
/vol/hitz/hitz/users/bcoates/matlab/sf2/PLL_Control/vectors
-------------------------------------------------------------------------------------------------------------------------
I've added flow.mdl to the LIBFILES and the added correct
paths.
The EPIC part is the part that uses the hspice netlister that I mentioned
before. Here I have told it to make a netlist for the thing called PLL_Control
( the second one) in the libname flow, also it gets the test vectors from the
path: /vol/hitz/hitz/users/bcoates/matlab/sf2/PLL_Control/vectors that
start with the name PLL_Control (the first one) and
puts them a directory named /epicrun/PLL_Control/