Logic Verification Front to Back, via Fred's Script

First thing you have to do is have a design in simulink that you are prepared to verify. NOTE: this does not totally verify timing, this uses EPIC timemill simulation on the schematic netlist, which is only a logic verification and loosely verifies timing.

I will run you through a example of a block that was in Paul's SCR1 chip that was tested for logic.  The Idea here is that each major block is tested separately for logic verification. It is possible to do the whole design, but this take a long time and is harder to debug if there is a problem. So the Filter100 block is the one we will test.

Creating vectors


The first thing we did is create vectors in Simulink for the Filter100 block. There are two ways to do this, which are essentially the same. 
One way is to run a simulation of the whole design - SCF1 - and  take vectors going into and out of the block you desire to test - Filter100.  
The other way is to make a entire new design with only Filter100 in it, and put random signals going in to it. 
See \\hitz\Users\bcoates\matlab\filter\Filter100\   in this directory there is a simulink file called filter100_test - this contains the Filter100 block that has been cut and pasted from the SCR1 design to here and you see random sine waves going in to it 

Also you see that there are the Fixed pt gateways going in and out - these are needed to make sure that the data types are correct. If you double click on one of the Gateway In blocks you will see that it is of data type sfrac(8). This is to force the signal to be of type sfrac(8). You also have the Gateway out blocks that are needed to send the vectors to the workspace. 

If you double click on the GateWay outs the should look like this: 

If you double click on the to workspace it should look like this:
We see that the variable name is set to 'Z3' as a matrix.

If you goto the menu item Simulation-> Simulation Parameters you will see this:

You see the stop time is 4000e-9, this will give you 4000e-9/40e-9 = 100 vector values. You can change this. for more or less.

Next you have to save the vectors into files with the right name. Here is where fred page explains more. But i will make it easier.

Make a .m file that looks like this


This saves the vectors A1,A2,A3,A4,Z1,Z2,Z3,Z4 as those file names. The file name contains lots of info:
Blockname
Input/Output name
DataType name (sfrac or uint)
DataType numbers (9.0 means that it was sfrac(9,0) Mantissa and Guard 
Is it In or Out?
Call it a .mat file.

You also need the flags -ASCII and -DOUBLE for it to work.
So you make this file then in the matlab command window you run it by typing "SaveFilter100" it will then save these files to your pwd. You need to remember where they are. I put them in a separate directory \\hitz\Users\bcoates\matlab\filter\Filter100\vectors

Now you are ready to run the whole thing

Runing ICMAKE 

The Design I ran through Icmake is different and is located at \\hitz\Users\bcoates\matlab\filter\Filter100\  and it called test.mdl
This path will be needed in the ICMAKEFILE when running icmake. 

This design is simple and does not have all the necessary parameters for floorplanning and pads etc.
It has the bare-bones to get a schematic netlist from the design.


Sample icmakefile:
----------------------------------------------------------------------------------------------------------------------------
DESIGN = test
SOURCEFILE = test.mdl
LIBFILES = fundamental.mdl route.mdl complex.mdl accumulators.mdl fixed_adders.mdl mux.mdl dec_filter_lib.mdl dec_filter_ext.mdl 
MDLPATH = /vol/hitz/vol1/designs/scr/scr_shadow/receiver/digital/precompiled /vol/hitz/vol1/designs/scr/scr_shadow/receiver/digi
tal/filter/ /vol/hitz/hitz/users/bcoates/matlab/filter/Filter100/
TOLERANCE = high

all: bcc elab ein buf sim

sim:
EPIC = Filter100 test test_Filter100 /vol/hitz/hitz/users/bcoates/matlab/filter/Filter100/vectors/
------------------------------------------------------------------------------------------------------------------------------
This icmakefile only makes the steps to make the hspice netlist and run the verification - it does not do the floorplan stuff.

Note - The EPIC step is designed to take any schematic out of any library on the hierarchy, We could have run the bigger design of SCR1 or SCF1 and only chosen to get the schematic of Filter100 block.  below explains this alittle:

The part we are going to focus on is the EPIC part under sim: 

After the flow is run there is a directory in your icmake run directory called 'epicrun' In this directory there is a sub directory called Filter100 - in this directory all the vectors are placed and the netlist is placed and the epic files are placed.

The Flow automactily runs Fred's script m2epic_vec.pl  
To run fred's script over by yourself, all it needs is the spice netlist and it need the vectors to be present in the working directory.
You type:

%m2epic_vec Filter100.sp

Fred script creates many files that are needed to run epic. 

to run the timemill simulation type:

%source verify.epi

this will run start the simulation. the file verify looks like this: 
timemill -n Filter100.sp input.epi -p /tools/unicad/local/epic_models/hcmos7_1v_nom -t 4058 -c config.epi 

You can see it uses the input.epi file, config.epi file, netlist, technology file, and set simulation time (4058ns)
When you run it you will see if there are errors an then it reports total errors. There should be none.
To view wave forms start ->tubroWave (just type it) open timemill.out file (this is pretty straight forward)

If there are errors you can try some things that I had to do. If you look at the config.epi file:
--------------------------------------
print_node_logic bclk[0] bclk[1] a1[8-0] a2[8-0] a3[8-0] a4[8-0] z1[8-0] z2[8-0] z3[8-0] z4[8-0] 
print_node_v bclk[0] bclk[1] a1[8-0] a2[8-0] a3[8-0] a4[8-0] z1[8-0] z2[8-0] z3[8-0] z4[8-0] 
print_node_logic Dummyz1[8-0] Dummyz2[8-0] Dummyz3[8-0] Dummyz4[8-0] 
print_node_logic *
You add these lines: not this one though
set_node_ic *reg*s1 0.0V
set_node_ic *reg*m4 1.0V
set_node_ic *s1* 0.0V
set_node_ic *m4* 1.0V
-----------------------------------
This sets initial conditions of all the nodes to zero in any registers.  

Also in the file input.epi: these are the first two lines only.
(is=clk) (en=CLOCK1) (ot=iclk[0],mclk[0]) (ov=1,1) (sv=18.5,23,40,1,1);
(is=clk) (en=CLOCK2) (ot=iclk[1],mclk[1]) (ov=0,0) (sv=21.5,17,40,1,1);
I have changed the "sv" numbers to widen the overlap time. 
normally it looks like this:
(is=clk) (en=CLOCK1) (ot=bclk[0],mclk[0]) (ov=1,1) (sv=19.5,21,40,1,1);
(is=clk) (en=CLOCK2) (ot=bclk[1],mclk[1]) (ov=0,0) (sv=20.5,19,40,1,1);