Logic Verification Flow

What's contained in this page?

This page gives a brief description of the most current timing verification flow between a Matlab SIMULINK design and the subsequent HSPICE netlist produced by...(ta da) Rhett Davis' design flow.  Here's what you'll need:

• Matlab SIMULINK design (fixed point)
• HSPICE netlist of the SIMULINK design
• EPIC's TimeMill tool  (brief tutorial)

How do I verify my SIMULINK design?  Or better yet, how do I verify my module generator?

1. First, you need to generate some input and output test vectors in SIMULINK.
2. Next, you need to save those vectors into files and then transfer them over into a UNIX environment if you're not already in one.  There should be one file per input/output variable and the files should be named with the following convention:

    filename:  "<netlist name>.<variable name>.<data type>.<data width>.<data radix>.<in/out>.mat"

• <netlist name> -the name of the netlist you plan to test.   i.e.  if you're netlist name is "adder.sp" then all of your input and output vectors for that netlist should begin with "adder.<var name>.<etc... "
• <variable name> -the name of the variable used in SIMULINK.   This should correspond to a node or set of nodes in the uppermost level of the HSPICE netlist.
• <data type> -exactly what it says... the data type of the variable as used in SIMULINK.  Currently, only sfrac() and uint() data types are supported
• <data width> -the bit width of the variable
• <data radix> -the number of bits to the right of the sign bit (if there is one) or MSB that the decimal point is.
• <in/out> -specifies whether the vector is an input or output.   Thus, all of these vector files should either end with ".in.mat" or ".out.mat".

   Sample:  Take the case of a fixed point adder.  Let the inputs to the adder be ia and ib.   Let the sum output be iz.  As declared in Matlab, let's assume the data types for ia, ib & iz are sfrac(9,3), sfrac(8,2) and sfrac(10,4) respectively.  Also, let's assume the name of the HSPICE netlist is called "adder.sp".  The corresponding vector file names for these variables should be:

For ia:   "adder.ia.sfrac.9.3.in.mat"

For ib:    "adder.ib.sfrac.8.2.in.mat"

For iz:    "adder.iz.sfrac.10.4.out.mat"

3. Once you have the vector files, place them all in the same directory.  You can now run the timing verification script(s) to check your design.  The following is a list of the scripts available & their description/usage.  All of the following scripts can be found under the "/tools/designs/SCR1/verification/timing/scripts" directory.

• <m2epic_vec.pl> - This file will read in the vector files and write the necessary epic files needed to run the simulation.

• USAGE:  m2epic_vec.pl <netlist file> <matlab dir> <output dir> <tech file> <period> <clk node>
  • <netlist file> - name of the netlist to be simulated (ex:   "adder.sp")
  • <matlab dir> - directory where the matlab vector files are (default: current directory)
  • <output dir> - directory where you want the epic files to go.  Should be where your HSPICE netlist file is.  (default: <matlab dir>)
  • <tech file> - the technology file you want to use for simulation.  (The default file is:  "/tools/unicad/local/epic_models/hcmos7_1v_nom")
  • <period> - period of the clock cycle in nanoseconds (default: 40ns)
  • <clk node> - the name of the clock node(s) in your design (current default: n0 & n1)
• OUTPUT:  This script generates up to 6 files for TimeMill simulation.
  • "config.epi" - File indicating how TimeMill runs and what will be displayed.   (Currently, this only prints out the states of all input & output nodes as well as the clocks)
  • "input.epi" - File containing all of the independent sources.
  • "inputvec.epi" - File containing all of the input vectors as referenced by "input.epi"
  • "outputvec.epi" - File containing all of the output vectors to be checked & when they should be checked
  • "dummyvec.epi" - File containing all of the output vectors as dummy inputs so that they can be viewed using "TurboWave" along side actual outputs
  • "verify.epi" - File containing the command line to run the TimeMill simulation (you can just source this file to run TimeMill once the script has generated the files)

• <m2wv.pl> - This does exactly the same thing as "m2epic_vec.pl" but all of the input & output vectors in the *vec.epi files will be written in binary.

• <chk_err_tm.pl> - This file will read in the timemill output file, "timemill.err", and report the number of actual errors.

• USAGE:  chk_err_tm.pl <latency> <period>
  • <latency> - number of clock periods +1 before the output should be defined & steady (default: 0)
• <period> - the period of the clock in nanoseconds (default: 40ns)

• OUTPUT:  Prints the number of unexpected errors to STDOUT.

• <verify.pl> - This file will call "m2epic_vec.pl" , run TimeMill and "chk_err_tm.pl" to check the design.  The arguments are the same as in the individual functions alone

• USAGE: verify.pl <netlist file> <matlab dir> <output dir> <tech file> <period> <clk node> <latency>

4. To view the actual waveforms for the simulation, run turboWave at the UNIX prompt and open the "timemill.out" file in your run directory.  ( Ex:   unix_prompt> turboWave &)

Fred Chen

chenff@eecs.berkeley.edu