SSHAFT (IC Design Flow Group)

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Related Research Groups:
BEE
Receiver Algorithms]

last modified 07/01/2002

We are investigating an optimal design flow for communication ICs through the use of scripting and a purely top-down methodology.  Our flow allows system designers to create ICs that exhibit acceptable performance and consume minimal power without the need to cross abstraction boundaries. 

System designers concoct a design in SIMULINK, and our design flow will perform the subsequent steps to obtain a netlist, perform placement and routing, and obtain a layout that can be sent to foundries for fabrication.  In addition, designers will also be able to quickly obtain reliable estimates for power, area, and delay through a separate characterization flow.

This web page will allow you to learn more about the SSHAFT project and the people involved.  SSHAFT has precipitated new research ideas in the areas of system architecture, rapid prototyping, algorithms, low-energy circuit design, clocking and timing, circuit characterization, etc.  An example of this innovative push is the inception of the Biggascale Emulation Engine, or BEE project that utilizes multiple FPGA's on a board to aid in the rapid prototyping of RF and baseband communication systems.

You can find out more about the concept and theory of our design flow by checking out the following links:

• Design Flow Concept Slides [PowerPoint - 358K]
• Design Flow Overview [PowerPoint - 335K]

To contact SSHAFT, you can send email to:  icdf@bwrc.eecs.berkeley.edu

SSHAFT is a development of the Berkeley Wireless Research Center.