last modified 4/25/00
This page defines all of the parameters to be included in Simulink subsystem masks which drive the design flow. The top-level parameter is bjcType. See the Simulink Design Manifesto more more details.
If defined for an ICMacro, two-phase clock pins will be added to the cell definition and connected to the default clock driver. The pin will be named according to the variable's value i.e. a value of BCLK will give pins named BCLK<0> and BCLK<1>.
If defined for an ICMacro (or ICWire), the value provides a comma-separated list of mask variables which distiguish the eventual EDIF cell definition (or net definition) from other cells (nets) with the same input and output ports. A good example would be a mask variable which distinguishes an adder cell as ripple-carry or carry-bypass
Required Parameters: bjcDistPropType
A comma-separated list which provides the types for the list of mask variables given in bjcDistProp.
Possible Values:
- IsInt - the variable's value is an integer
- IsVal - the variable's value is some other value (probably floating point)
Default Value: ? (ask Hayden...)
Specifies the Simulink Fixed-Point type of subsystem input port (e.g. bjcPortTypeIn1, bjcPortTypeIn2, etc.). Required for all ICDesign input ports.
Possible Values: sfrac(x), sfrac(x,y), ufrac(x), ufrac(x,y), sint(x), uint(x)
Default Value: none
Specifies the Simulink Fixed-Point type of subsystem output port (e.g. bjcPortTypeOut1, bjcPortTypeOut2, etc.). Required for all ICMacro output ports.
Possible Values: sfrac(x), sfrac(x,y), ufrac(x), ufrac(x,y), sint(x), uint(x)
Default Value: none
The top-level parameter which determines how the design flow will attempt to process the block.
Must take one of the following values:
- ICDesign
Signifies the the underlying system will be traversed.
Required Parameters: bjcPortTypeIn# bjcViewName- ICMacro
Signifies that the system underlying the subsystem mask will not be traversed to fully specify the subsystem at the functional, signal, and circuit levels.
Required Parameters: bjcView_ElaborationType bjcPortTypeOut# bjcViewName
Optional Parameters: bjcAddClk, bjcDistProp, bjcView_SeparateAbgen- ICWire
Signifies that the mask represents a wiring construct which will not correspond to any cells or transistors in the physical design.
Required Parameters: none
Optional Parameters: bjcDistProp
For an ICMacro with a bjcViewName of abstract, specifies the highest metal layer for which the abstract will have a blanket obstruction.
Possible Values: 1-6
Default Value: 2
Specifies the cell name of the cell to be copied when elaborating an ICMacro with the bjcView_ElaborationType of Block.
Specifies the library name of the cell to be copied when elaborating an ICMacro with the bjcView_ElaborationType of Block.
Specifies the port name for which the load capacitance will be found when elaborating an ICMacro with the bjcView_ElaborationType of Buffer.
Specifies the margin (in nanometers) between the prBoundary and all instances/rows when performing boundary compaction during floor-planning.
Default Value: 2000
Specifies the margin (in nanometers) between instances/rows and other instances/rows when performing a distribution/compaction during floor-planning.
Default Value: 2000
Specifies whether boundary pin optimization will be performed by connectivity in higher levels of the hierarchy or by pins positions in lower levels of the hierarchy. Only subsystems with many densely packed modules should optimize pins based on lower level pin positions.
Possible Values: Higher, Lower
Defaule Value: Higher
Determines how an IC Macro will be elaborated.
Must take one of the following values:
- Block
Required Parameters: bjcView_BlockLibName bjcView_BlockCellName bjcView_AbsMetalObs- Buffer
Required Parameters: bjcView_ModuleName bjcView_ModuleArgs bjcViewBufferedPortName bjcView_AbsMetalObs- Module
Required Parameters: bjcView_ModuleName bjcView_ModuleArgs bjcView_AbsMetalObs- Stateflow
Required Parameters: bjcView_StateflowChart bjcView_StateflowMDLFile- VHDL
Required Parameters: bjcView_SourceFile bjcView_EntityName
Specifies the name of the top-level entity to be syntheized during elaboration of an ICMacro with the bjcView_ElaborationType of VHDL.
For an ICMacro with the bjcView_ElaborationType of Module, specifies the arguments to be passed to the module generator. This string is coded to get around EDIF syntax technicalities... more later on how to write this code.
Specifies the name of the Module to be generated for an ICMacro with the bjcView_ElaborationType of Module.
Specifies the direction for pad/pin order given in the Ring Constraint File. The constraint file allows specification of an order of pads/pins on each side (top, bottom, left, right) of a cell, but does not include a means of specifying what direction should be applied to that order. This parameter allows us to do just that.
Possible Values:
- UR - (up & right) Pads/pins on the left and right sides will be placed in order from bottom to top. Those on the top and bottom will be placed in order from left to right.
- DL - (down & left) Pads/pins on the left and right sides will be placed in order from top to bottom. Those on the top and bottom will be placed in order from right to left.
- CCW - (counter-clockwise) Pads/Pins on all sides will be placed in order counter-clockwise around the cell.
- CW - (clockwise) Pads/pins on all sides will be placed in order clockwise around the cell.
Default Value: UR
Specifies the path to the constraint file which determines how the I/O pins or pads will be placed on the boundary. A placement based on a constraint file overrides any automatic pin optimizations (see bjcView_dpPinOptDirection).
If no file is specified, or if the specified file does not extist, then the flow will halt, and a skeleton file will be created (during the rte step).
Required Parameters: bjcView_RingType, bjcView_RingConstraintDirection
Specifies whether the I/O ring for a cell will be pads or pins. Only a cell with the bjcType ICDesign may have a pad ring. All other cells are only allowed to have pin rings.
Possible Values: Pin, Pad
Default Value: Pin
If defined (and set to some non-empty value) for an ICMacro with an elaboration type of Module, Buffer, or Block, the abstract will be generated by a separate Cadence Design Framework II process. This parameter was added to circumvent an apparent bug in Cadence's Abgen program and is intended for use with large modules (like the multiplier and barrel shifter).
Specifies the full path of the VHDL source code file to be synthesized to elaborate an ICMacro with the bjcView_ElaborationType of VHDL.
Specifies the chart name of the Stateflow system inside the subsystem which will be synthesized for an ICMacro with the bjcView_ElaborationType of Stateflow.
Specifies the name of the MDL file which contains the Stateflow chart to be synthesized for an ICMacro with the bjcView_ElaborationType of Stateflow.
Specifies the view name that will appear in the output EDIF file for this cell. This value shoud be "abstract" for all ICMacros which do not require floor-planning, and "autoLayout" for all cells that do require floor-planning. At present, this corresponds to the following values:
bjcType bjcView_ElaborationType bjcViewName ICDesign n/a autoLayout ICMacro Block abstract Buffer abstract Module abstract Stateflow autoLayout VHDL autoLayout
Default Value: autoLayout
maintained by Rhett Davis
wrdavis@eecs.berkeley.edu