INSECTA (IC Design Flow Group)

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last modified 11/05/2004

Integrated Systems Environment for Configurable Technologies and ASICs

We are investigating an optimal design flow for communication ICs through the use of scripting and a purely top-down methodology.  Using a single high-level block diagram-based input description, designers can develop an SOC design, and map the result to a cycle and bit accurate FPGA or ASIC implementation. 

System designers prepare a design in SIMULINK using the Xilinx System Generator library components, and our design flow will produce a netlist which can be retargeted to either an FPGA platform or a custom ASIC.  By maintaining cycle and bit-accuracy between the high-level description, an intermediate VHDL description, and resulting bitmaps or ASIC layouts, the algorithm designer can participate early on in critical implementation decisions, and optimize algorithms to meet performance, power and area constraints.

To contact the INSECTA development team, you can send email to:  icdf@bwrc.eecs.berkeley.edu

INSECTA is a development of the Berkeley Wireless Research Center, with roots in the SSHAFT ASIC-specific Simulink to Silicon design flow.