The algorithms used by communication systems are typically specified as floating-point (infinite precision) operations.  On the other hand, digital VLSI implementations of these algorithms rely on fixed-point (finite precision) approximations to reduce cost of hardware while increasing throughput rates.  One essential step of top-down design flow is to determine the fixed-point data type of each signal node, namely the word-length, truncation mode and overflow mode.  However conventional approaches are typically both time-consuming and error-prone since ad-hoc assignments of fixed-point data type are performed manually and iteratively. 

This work proposes a floating-point to fixed-point conversion (FFC) methodology for digital VLSI signal processing systems, based on a statistical approach and global optimization which allows a high degree of automation.  A completely automated FFC tool based on the proposed methodology is implemented, and applied on a number of communication systems.

System designers concoct a design in SIMULINK using large word-lengths, and our design flow will perform the subsequent steps to resolve connectivity, perform grouping, estimate hardware, run simulations, do optimization and output fixed-point system.  In addition, designers will also be able to quickly obtain reliable estimates for area.  The fixed-point system becomes the input of BEE/SSHAFT design  flow.

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Contact: ccshi@bwrc.eecs.berkeley.edu