Vinson Lee

November 8, 1999

Comparison of SA-110 and SA-1100

1.0 Changes to the SA-110 Core for the SA-1100

1.1 Data cache reduced from 16 Kbyte to 8 Kbyte

The SA-1100 has an 8 Kbyte write-back data cache (Dcache) with 256 lines of 32-byte blocks and 32-way associativity. The cache is read allocate with round-robin replacement.

1.2 Read buffer added (nonblocking)

The SA-1100 has a four-entry software-programmable read buffer capable of loading 1, 4, or 8 words of data per entry. This facility permits software to increase performance of critical loop code by prefetching data into the buffer for use at a later time without blocking the operation of the processor. Software can flush either a single entry or the entire buffer.

1.3 Mini data cache added that allocates data based on MMU settings

The SA-1100 minicache is a 512-byte write-back cache and provides an alternate caching structure for dealing with large data structures that could thrash the main data cache.

1.4 Debug support added

Breakpoints allow the user to stop the processor execution after seeing a specific reference in either the instruction or data streams. Execution then proceeds to an exception routine during which the user may examine the internal state of the machine.

1.4.1 Instruction Breakpoint

The instruction breakpoint allows the user to stop the processor execution after the execution of an instruction at a selected address. The selected address is programmed into the instruction breakpoint address and control register (IBCR) by way of the Breakpoints register (coprocessor 15, register 14). When the breakpoint is enabled and the fetched instruction’s address matches the selected address, a prefetch abort exception is taken.

1.4.2 Data Breakpoint

The data breakpoint allows the user to stop the processor execution after a load or store operation to a particular address. The data breakpoint address is programmed into the data breakpoint address register (DBAR). For stores, the breakpoint condition may also be programmed to include a particular data pattern as well as the reference address. The data value is programmed by way of the data breakpoint value register (DBVR) and the data breakpoint mask register (DBMR), which determines which bits are to be compared. Breakpoints on loads are permitted only through an address match. Breakpoints and enabled through the data breakpoint control register (DBCR). When a breakpoint is taken, the processor takes a data abort exception. The BAR, DBVR, and DBMR are loaded by way of the Breakpoints register (coprocessor 15, register 14).

1.5 Process ID register added

Register 13 of the Cache and MMU Control Registers (Coprocessor 15) is now the Process ID (PID) registers. The SA-1100 supports the remapping of virtual addresses through this register.

In the SA-110, Register 13 of Coprocessor 15 is reserved and accessing this register causes unpredictable results.

1.6 Interrupt vector address adjust capability added

Bit 13 of the Control register (bit 13, register 1, coprocessor 15) is the virtual interrupt vector adjust bit. When this bit is 0, the base address of interrupt vectors is 0x000_0000. When this bit is 1, the base address of interrupt vectors is 0xFFFF_0000.

In the SA-110, bit 13 of the Control register is unused. Reads from this bit are undefined and writes are ignored.

2.0 Additional Features Built into SA-1100 Chipset

2.1 Memory and PCMCIA control module (MPCM)

The SA-1100 memory interface supports three interfaces and is programmable through the memory interface configuration registers.

2.1.1 DRAM Memory Interface

The dynamic memory interface supports four 32-bit wide banks of fast-page or EDO asynchronous DRAMs.

2.1.2 Static Memory Interface

The static memory interface has four chip selects and 26 bits of byte address for access of up to 64 Mbyte of memory in each of four banks. Each chip select is individually programmable for selecting nonburst ROM, burst ROM, Flash EPROM, or asynchronous SRAM.

2.1.3 PCMCIA Interface

The PCMCIA interface provides control signals to support a single PCMCIA card slot with additional hooks to support two slots.

2.2 System control module (SCM)

2.2.1 General-Purpose I/O

There SA-1100 provides 28 general-purpose I/O (GPIO) port pins for use in generating and capturing application-specific input and output signals. Each pin is programmable as an input or output and as an interrupt source.

2.2.2 Interrupt Controller

The interrupt controller provides masking capability for all interrupt sources and combines them into their final state, either an FIQ or IRQ processor interrupt.

2.2.3 Real-Time Clock

The SA-1100 contains a real-time clock that provides a general-purpose real-time reference for use by the system. The time is stored in the real-time clock counter register (RCNR). There also exists a 32-bit alarm register (RTAR) which may be used to compare against the RCNR to generate CPU interrupts.

2.2.4 Operating System Timer

The SA-1100 contains a 32-bit operating system timer that is clocked by the 3.6864-MHz oscillator. Time is stored in the operating system count register (OSCR). The OS timer also contains four 32-bit match registers (OSMR[3:0]), each of which can be written and read by the user. When the value in the OSCR matches the value within any of the match registers, and the interrupt enable bit is set, the corresponding bit in the OSSR is set. These bits are also routed to the interrupt controller where they can be programmed to cause an interrupt. OSMR[3] also serves as a watchdog match register that resets the SA-1100 when a match occurs.

2.2.5 Power Manager

The power management logic that controls the transition between three different modes of operation: run (full-on), idle (power-down), and sleep (power-down). Idle mode is entered via software. Sleep mode is entered either via software or by asserting one of two input pins that indicate a power supply fault. Idle mode is exited through an interrupt. Sleep mode is exited through a preprogrammed wake-up condition.

2.2.6 Reset Manager

The reset controller manages the various reset sources within the SA-1100. There are four types of reset: hardware, software, watchdog, and sleep.

2.3 Peripheral control module (PCM)

The peripheral units include one parallel data port to drive an LCD display, one synchronous serial port, and four asynchronous serial ports that implement different serial protocol standards.

2.3.1 DMA Controller

The DMA controller consists of six independent DMA channels and acts as the gateway to the serial ports. Each channel can be configured to service any of the serial controllers but two channels are required to service a full-duplex serial controller. The DMA controller is intended to relieve the processor of the interrupt overhead in servicing these ports with programmed I/O. The DMA controller performs context switches based on whether a channel is active, whether its target device is currently requesting service, and where that channel lies in the priority scheme.

2.3.2 LCD Controller

The SA-1100’s LCD controller has three types of displays:

Passive Color Mode - Supports a total of 3375 possible colors, allowing any 256 colors to be displayed each frame.
Active Color Mode - Supports up to 65536 colors (16-bit).
Passive Monochrome Mode - Supports 15 gray-scale levels.

Display sizes up to 1024 x 1024 pixels are supported.

2.3.3. Serial Port 0 – USB Device Controller

Serial port 0 is a universal serial bus device controller (UDC) that supports three endpoints and can operate half-duplex at a baud rate of 12 Mbps (slave only, not a host or hub controller).

2.3.4 Serial Port 1 – SDLC/UART

Serial port 1 is a combination synchronous data link controller (SDLC) and universal asynchronous receiver/transmitter (UART) serial controller. The user can configure it to perform one of the two functions, but operation of both modes using serial port 1’s pins cannot occur simultaneously (SDLC transmit and UART receive). For both protocols, serial port 1 can operate at baud rates from 56.24 bps to 230.4 Kbps.

2.3.5 Serial Port 2 - Infrared Communications Port (ICP)

The infrared communications port (ICP) operates at half-duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers. The ICP supports both the original IrDA standard with speeds up to 115.2 Kbps as well as the newer 4-Mbps standard.

2.3.6 Serial Port 3 – UART

Serial port 3 is a general-purpose, full-duplex, universal asynchronous receiver/transmitter that supports much of the functionality of the 16550 protocol. It can operate at baud rates from 56.24 bps to 230.4 Kbps. It supports 7 or 8 bits of data (odd, even, or no parity), one start bit, either one or two stop bits, and can transmit a continuous break signal.

2.3.7 Serial Port 4 – MCP / SSP

Serial port 4 contains two separate full-duplex synchronous serial interfaces.

The multimedia communications port (MCP) provides an interface to the Philips UCB1100 and UCB1200 codecs. Both devices have an audio codec, a telecom codec, a touch-screen interface, four general-purpose analog-to-digital converter inputs, and ten programmable digital I/O lines. The MCP interface is used by the SA-1100 both to input and output digital data to and from the codec, and to configure and acquire status information from the codecs’ 16 registers.

The synchronous serial port (SSP) is used to interface to a variety of analog-to-digital converters, audio and telecom codecs, memory chips, and keypad controllers as well as other miscellaneous serial devices. The SSP supports the National Microwire and Texas Instruments synchronous serial protocols as well as a subset of the Motorola serial peripheral interface (SPI) protocol.

2.4 SA-1100 Crystal Oscillators

There are two on-chip oscillators for clock sources. The first oscillator is connected to at 3.684-MHz crystal. The output of this oscillator is used to generate baud rates for the serial ports.

The second oscillator is connected to a 32.768-kHz crystal and its output clocks the power management controller and the real-time clock.