PRTB - Xilinx Libs

ARM Interface
Cut and Paste	External Connection Blocks	Major Functional Blocks	Radio Interfaces	Generic Support Blocks
palette	io	datapaths	bluetooth	misc
		fifo	proxim	state
		tdma		time

Block Name	Description	Notes
extmem_flash	Interface to the 16Kx8 flash memory dedicated to the Xilinx.	Read, program, erase, and init. Software interface under development.
extmem_sram_16	Interface to the 64Kx16 SRAM dedicated to the Xilinx.	See the External SRAM Interface Data Sheet for details.
extmem_sram_32	Interface to the 32Kx32 SRAM dedicated to the Xilinx.	Software interface under development.
pins_gpio	ARM GPIO pins.	.
pins_radio_bluetooth	Bluetooth radio pins.	This block is included in the Bluetooth controller block. Normally, you would use the controller block rather than access the radio directly.
pins_radio_proxim	Proxim radio pins.	This block is included in the Proxim controller block. Normally, you would use the controller block rather than access the radio directly.
pins_tp_flash	Test points.	Available ONLY if the Xilinx flash memory is NOT used.
pins_tp_sram	Test points.	Available ONLY if the Xilinx SRAM is NOT used.
pins_interrupt	IRQ and FIQ outputs.	The ARM supports user-defined IRQ and FIQ interrupt service routines. All of the complex library blocks that use interrupts include this block. If you are designing a custom block that issues one or more interrupt, instantiate this block inside your custom block or in the top level workspace and attach one of the inputs (IRQ or FIQ) to the interrupt source. See the discussion on FIQ and IRQ.
pins_xio_all	All Xilinx general purpose I/O pins.	Can be input, output, or tristate. Can't be used with the Bluetooth radio and can only be used with the Proxim radio if the RSSI A/D is removed from its socket on the Proxim adapter board.
pins_xio_bluetooth	Xilinx general purpose I/O pins for Bluetooth apps.	Can be input, output, or tristate.
pins_xio_proxim	Xilinx general purpose I/O pins for Proxim apps.	Can be input, output, or tristate.

Block Name	Description	Notes	ARM Library Support
datapaths	Full 32 bit Tx/Rx datapaths.	Includes full support for independent Tx and Rx datapaths: FIFOs, CRC, line balancing, interrupt support, serial to parallel and parallel to serial conversion, FIFO status outputs, and loopback capability.	misc
datapaths_txfifobypass	Full 32 bit Tx/Rx datapaths with Tx FIFO bypassing.	Identical to datapaths with the addition of a separate 32 bit data input that bypasses the Tx FIFO, going directly to the parallel to serial converter. Rx FIFO bypass is included in both datapath variants.	misc
rx_datapath	Complete 32 bit receive datapath.	Includes FIFO, CRC, linebalance, deserializer, and interrupt support for Rx.
rx_deserializer	32 bit serial to parallel converter.	Simple serial left shift register with parallel outputs. No control - designed to be free-running.
tx_datapath	Complete 32 bit transmit datapath.	Includes FIFO, CRC, linebalance, serializer, and interrupt support for Rx.
tx_datapath_fifobypass	Complete 32 bit transmit datapath.	Variant of tx_datapath with FIFO bypass input.
tx_serializer	32 bit parallel to serial converter.	Simple serial left shift register with parallel inputs, with load control
crc	8 bit CRC.	Polynomial =
linebalance	Serial line balancer.	Provides a DC balance to a serial Tx data stream, or recovers the balanced signal from an Rx data stream. Can be disabled. Is included in all library data path blocks.
datastream_16	16 bit programmable data stream.	Generates a serial data stream, repeating every 16 bits. Value of the data is programmable from the ARM by assigning the low 16 bits of an I/O block port to the data input. Intended for testing purposes.
datastream_64	64 bit programmable data stream.	Generates a serial data stream, repeating every 64 bits. Value of the data is programmable from the ARM by assigning two I/O block ports to the data inputs. Intended for testing purposes.

Block Name Description Notes

fifo_32x32 32 deep by 32 wide synchronous FIFO. See the FIFO Data Sheet for details.

fifo_32x8 32 deep by 8 wide synchronous FIFO.

Block Name Description Notes ARM
Library
Support

tdmablock
Complete TDMA protocol block. TDMA
Channels

Block Name Description Notes

timeblock 1 MHz clock and 16 bit programmable timer. These blocks have not been used for a while. Legacy from InfoPad. Should work OK, but might require some tweaking.

timebase 8KHz clock (125us)

multitime 1) Programmable 6 bit divider for the 20MHz master clock
2) Programmable 4 bit divider for the 20MHz master clock with an optional stall.
3) 1MHz clock.
4) Programmable timer.

ecb4cle 4 bit binary counter with clear, parallel load, and enable. These devices are built up from the XC4000 library. The bit widths are not available in the standard library (except the 4 bit counter), but the behavior is identical otherwise. The 4 bit counter combines individual counter outputs into a bus in order to conform with the bus interface.
The RST input is synchronous with the clock while the CLR input is asynchronous.

ecb4re 4 bit binary counter with reset and enable.

ecb5cle 5 bit binary counter with clear, parallel load, and enable

ecb5re 5 bit binary counter with reset and enable

ecb5ce 5 bit binary counter with clear and enable

ecb6cle 6 bit binary counter with clear, parallel load, and enable.

ecb6re 6 bit binary counter with reset and enable.

ecb9cle 9 bit binary counter with clear, parallel load, and enable.

ecb9re 9 bit binary counter with reset and enable.

ecb10cle 10 bit binary counter with clear, parallel load, and enable.

ecb10re 9 bit binary counter with reset and enable.

ecb13rle 13 bit binary counter with reset, parallel load, and enable.

ecb13cle 13 bit binary counter with clear, parallel load, and enable.

ecb14cle 14 bit binary counter with clear, parallel load, and enable.

fjk4 4 bit J-K flip-flop.

fjk16 16 bit J-K flip-flop.

fjk20 20 bit J-K flip-flop.

fjk32 32 bit J-K flip-flop.

fd2re 2 bit D flip-flop with reset and enable.

fd7ce 7 bit D flip-flop with clear and enable.

fd32re 32 bit D flip-flop with reset and enable.

elatch 1 bit Earle latch. Very simple transparent latches suitable for a wide range of applications where logic complexity is a problem. When the G = 1, Q = D. when G = 0, Q = Q'

elatch4 4 bit Earle latch.

elatch5 5 bit Earle latch.

elatch6 6 bit Earle latch.

elatch8 8 bit Earle latch.

byteclk Byte counter. Emits a one clock cycle wide pulse every 8 cycles. Includes a synchronization input that loads a preset value when taken low.

wordclk Word counter. Emits a one clock cycle wide pulse every 32 cycles. Includes a synchronization input that loads a preset value when taken low. Also has a byte clock output that emits a one clock cycle wide pulse every 8 cycles.

oneshot One-shot pulse shaper. Generates a single one-cycle pulse on the Q output when the D input goes from low to high. Will not generate another pulse until the input is taken low, then high again. Includes an asynchronous reset input.

halfshot_LL Pulse shaper with level sensitive set and reset inputs. Low-to-high transition on the D input generates a low-to-high transition on the Q output. Low-to-high transition on the R input generates a high-to-low transition on the Q output.
The terms edge and level in this context do not have the typical interpretation. Edge means the action occurs after a low-to-high transition and will NOT reoccur until the input is taken low, then high again. Level means that the action occurs whenever the input is high regardless of whether it has been taken low previously. All output transitions happen synchronously with the C (clock) input.

halfshot_EL Pulse shaper with edge sensitive set input and level sensitive reset input.

halfshot_LE Pulse shaper with level sensitive set input and edge sensitive reset input.

halfshot_EE Pulse shaper with edge sensitive set and reset inputs.

Block Name	Description
comp10	10 bit comparator
d4_16	4:16 demultiplexer
d5_20	5:20 demultiplexer
mux2x4	2:1 multiplexer, 12 bits wide
mux2x5	2:1 multiplexer, 12 bits wide
mux2x7	2:1 multiplexer, 12 bits wide
mux2x8	2:1 multiplexer, 12 bits wide
mux2x12	2:1 multiplexer, 12 bits wide
mux2x14	2:1 multiplexer, 14 bits wide
mux2x16	2:1 multiplexer, 16 bits wide
mux2x18	2:1 multiplexer, 18 bits wide
mux2x32	2:1 multiplexer, 32 bits wide
mux4x8	4:1 multiplexer, 8 bits wide
mux4x12	4:1 multiplexer, 12 bits wide
mux4x32	4:1 multiplexer, 32 bits wide
mux32x1	32:1 multiplexer, one bit wide

ecb4cle	4 bit binary counter with clear, parallel load, and enable.	These devices are built up from the XC4000 library. The bit widths are not available in the standard library (except the 4 bit counter), but the behavior is identical otherwise. The 4 bit counter combines individual counter outputs into a bus in order to conform with the bus interface. The RST input is synchronous with the clock while the CLR input is asynchronous.
ecb4re	4 bit binary counter with reset and enable.
ecb5cle	5 bit binary counter with clear, parallel load, and enable
ecb5re	5 bit binary counter with reset and enable
ecb5ce	5 bit binary counter with clear and enable
ecb6cle	6 bit binary counter with clear, parallel load, and enable.
ecb6re	6 bit binary counter with reset and enable.
ecb9cle	9 bit binary counter with clear, parallel load, and enable.
ecb9re	9 bit binary counter with reset and enable.
ecb10cle	10 bit binary counter with clear, parallel load, and enable.
ecb10re	9 bit binary counter with reset and enable.
ecb13rle	13 bit binary counter with reset, parallel load, and enable.
ecb13cle	13 bit binary counter with clear, parallel load, and enable.
ecb14cle	14 bit binary counter with clear, parallel load, and enable.
fjk4	4 bit J-K flip-flop.
fjk16	16 bit J-K flip-flop.
fjk20	20 bit J-K flip-flop.
fjk32	32 bit J-K flip-flop.
fd2re	2 bit D flip-flop with reset and enable.
fd7ce	7 bit D flip-flop with clear and enable.
fd32re	32 bit D flip-flop with reset and enable.
elatch	1 bit Earle latch.	Very simple transparent latches suitable for a wide range of applications where logic complexity is a problem. When the G = 1, Q = D. when G = 0, Q = Q'
elatch4	4 bit Earle latch.
elatch5	5 bit Earle latch.
elatch6	6 bit Earle latch.
elatch8	8 bit Earle latch.
byteclk	Byte counter.	Emits a one clock cycle wide pulse every 8 cycles. Includes a synchronization input that loads a preset value when taken low.
wordclk	Word counter.	Emits a one clock cycle wide pulse every 32 cycles. Includes a synchronization input that loads a preset value when taken low. Also has a byte clock output that emits a one clock cycle wide pulse every 8 cycles.
oneshot	One-shot pulse shaper.	Generates a single one-cycle pulse on the Q output when the D input goes from low to high. Will not generate another pulse until the input is taken low, then high again. Includes an asynchronous reset input.
halfshot_LL	Pulse shaper with level sensitive set and reset inputs.	Low-to-high transition on the D input generates a low-to-high transition on the Q output. Low-to-high transition on the R input generates a high-to-low transition on the Q output. The terms edge and level in this context do not have the typical interpretation. Edge means the action occurs after a low-to-high transition and will NOT reoccur until the input is taken low, then high again. Level means that the action occurs whenever the input is high regardless of whether it has been taken low previously. All output transitions happen synchronously with the C (clock) input.
halfshot_EL	Pulse shaper with edge sensitive set input and level sensitive reset input.
halfshot_LE	Pulse shaper with level sensitive set input and edge sensitive reset input.
halfshot_EE	Pulse shaper with edge sensitive set and reset inputs.

Xilinx Libraries and Circuit Blocks