PicoRadio Test Bed Workspace Setup:
Xilinx Project 

1. Install the default project
   
   
   • Go to <your workspace directory>\Xilinx.  
     
     
   • Double click on Xilinx_Project_Template.vpj.  It should start the Viewlogic Project Manager if WVOffice is installed. Check the list of libraries installed in C:\ at the bottom of the window.  If there is a red circle and slash in front, the Xilinx tools have not been installed.  
     
     
   • !!! THIS STEP IS CRITICAL !!! Select Edit/Project Directory, and change the path to <your workspace directory>\Xilinx. 
     
     
   • Select Save As from the File menu and save the template under a name of your choice.  
     
     
   • Delete Xilinx_Project_Template.vpj.

   Take a look at the list of paths in the Xilinx Project Manager window.  These are the available support libraries.  See Custom Xilinx Libraries for details.  You can extract modules and designs from these using ViewDraw, and include them in your design.

    

2. Create your new project
   
   
   • Start WVOffice from: Start menu/Programs/Workview Office/Workview Office.
     
     
   • Start ViewDraw (roll over the WVOffice icon bar to find it - it's red and white with a pencil or stylus in it).  
     
     
   • Click on the Open icon.  You will see a popup that has a list of subprojects on the left and toplevel_template.1 on the right. The list on the left corresponds to the Project Manager window, and toplevel_template.1 is the top hierarchical level of the default project.  
     
     
   • Click on one of these entries in the list on the left.  The right list is replaced with a set of names.  Each of these names represents a model that you can view or include in your top-level schematic as a symbol.  
     
     
   • Click on the topmost line in the left column to return to the original view.
     
     
   • Double-click on toplevel_template.1 
     
     
   • When the schematic appears, type a 'W' and enter a name for your design (DON'T include the .1 extension).  
     
     
   • Close the template schematic.
     
     
   • Open the one you just created.  This is the starting point for your Xilinx project.  The block on the bottom is standard for all designs. Build your circuit on this sheet using components from one of libraries in the list on the left side of the open dialog: xc4000, xc4000x, builtin, xbuiltin, and  logiblox are basic Xilinx libraries, the others are custom support libraries.

    

3. Customize the compilation path
   
   
   • Edit Makefile.  Modify subsection 1, and subsection 2 if needed. Instructions are in the Makefile.

    

4. Test the compilation path
   
   
   • Open a tcsh window and cd to <your workspace directory>/Xilinx.   This tcsh is very much like tcsh under Unix, with some minor exceptions.
     
     
   • Run make install.  If everything is correctly installed and modified, the compilation tool flow should complete without errors.  The final compilation step prints the message CREATING HEADER FILE FOR STANDALONE.   Errors are written to log files in <your workspace directory>/Xilinx/logs
     
     
   • Now, take a look in the compiled directory.  You should see two files.  Both should have the same base name, and the base name should be the same as your top level schematic.  One of them should have a .raw extension and the other should have a .h extension.  Go back to the ARM project and change the constants in application.h to the absolute path name to these files (you can use a mapped drive).  See ARM Project Setup step 3.

    

5. Optional: Install pre-existing VHDL files
   
   
   • If you have VHDL files, put them in <your workpace directory>\Xilinx\behv.  
     
     
   • In the behv directory, you'll find a file called fe_shell.txt.template.  For each .vhd file that you're adding, make one copy of fe_shell.txt.template.  Give the copy the same base name with extension .txt.  
     
     
   • Edit the .txt files and change the first line to match the VHDL design name.  The .vhd file base name must be the same as the VHDL design name.  
     
     
   • Open a tcsh window and cd to <your workspace directory>/Xilinx.  For each VHDL file, run the command vhdl2sym behv/<filename>    Include the extension.  This will create a Viewlogic symbol so that you can include the part in your top-level schematic.

    

6. Optional: Set up the simulation environment for VHDL
   
   
   • On the WVOffice toolbar, click the leftmost icon and select Add Program.  Browse to C:\WVOFFICE\vhdlmgr.exe, give it the description VHDL Manager.  Leave arguments blank.
     
     
   • Start the VHDL Manager.  You'll use the Library tab the most.
     
     
   • Create a new library to hold one or more .vhd files.  Call it something related to the collection of files.
     
     
   • Add the .vhd files to the new library (Library/Add Source File).
     
     
   • Compile the library (Analyze/...)
     
     
   • In <your workspace directory>/Xilinx rename vsslib.init.template to vsslib.ini.  Edit vsslib.ini.  Replace the first line with the path to your new library.
     

   The simulator will now recognize VHDL designs in the new library when they are embedded in a schematic via the symbol created in step 5.  If the VHDL is edited, you MUST rebuild the library.  This is a pain, and there should be a better way to do this.

Maintainer: Fred Burghardt
Modified: October 4, 2000