In current attempts at low-power, single-chip, integrated radio solutions, the analog circuitry tends to consume a majority of the total power. Tight RF requirements on the front-end receivers, and large transmit powers necessary for long distances and high signal to noise ratios, constrain a design with difficult, if not impossible, specifications to implement with very low power in a low-cost CMOS technology. While low-power digital techniques for large-scale designs exist and are being actively applied, no comparable techniques have emerged yet for the analog design components. Current trends suggest that the while the speed and energy efficiency of digital circuits will improve with the lower supplies and smaller geometries, analog circuits are actually hampered by the supply reduction. This suggests a sort of "Holy Grail" for radio design, which eliminates as much as possible the necessity for analog components. This radio would ideally convert the incoming antenna signal to a binary value and then perform all processing digitally, yielding an implementation with all of the benefits digital design has to offer (full integration, lower power, cheaper technology, robustness, the ability to implement complex algorithms such as adaption, maximum likelihood estimation, etc.) While current radio standards would require a very fast and high accuracy A/D, we believe that by using a pulse-based, ultra-wideband signaling scheme we can approach this fully-digital, fully-integrated radio; reducing both transmit power and the receiver's analog complexity beyond simply scaling a traditional narrowband transceiver. 

The focus of this research is the design of such a "fully-digital" single-chip radio transceiver. We assume no special or fixed building infrastructure; the radios will be able to communicate flexibly in both peer-to-peer or broadcast modes. The target cell-size is approximately 5-10 meters with a maximum of 32 active users at one time per cell. The anticipated bit-rate may be from 1kb/s to 1Mb/s (uncoded BER ~1e-3) and should gracefully scale with the power consumption. In addition, the ability to do some form of ranging or localization is a considered a necessity. As extreme low cost and high integration are desired, we are investigating PCB/circuit co-design for the antenna and matching elements, and targeting a generic, digital CMOS IC process for fabrication.

As opposed to traditional narrowband radios, Ultra-Wideband (UWB) is a wireless digital communication system exchanging data using short duration pulses. The complexity of the analog front-end in UWB is drastically reduced due to its intrinsic baseband transmission. Based on this simplification and the high spreading gain it possesses, UWB promises low-cost implementation with fine time resolution and high throughput at short distances without interfering with other existing wireless communication systems. However, the wideband nature of the front-end architecture leads to a totally different design methodology from traditional narrow-band systems. For example, if one employed the conventional narrow-band design approach, matching between the power amplifier and the antenna would be a big problem owing to the fact that it is extremely difficult to match accurately over a such a wide range of frequencies. In addition, we desire a high degree of integration, which requires an antenna on the order of centimeters in size. But, it is hard to attain efficient transmission bandwidth from DC to GHz with such a small antenna..

The focus of this research is to determine the methodology for co-designing an appropriate antenna suitable for efficient pulse transmission/generation and pulse reception with analog circuits that won’t induce signal dispersion (ISI, Inter-Symbol Interference) or further complicate the digital backend. Finite-Difference Time-Domain (FDTD) electromagnetic wave simulation will be used to characterize the antenna. While doing antenna/circuit co-design optimization, the way of combining FDTD and SPICE simulation will also be investigated.

    Because of the ultra-wide bandwidth of the transmitted signal, receiver design strategy has different interesting issues as opposed to narrowband systems. Given the fact that ultra wideband has several possible application areas, system-level explorations will be done in this research. First work will be focused on building a real time Simulink model which includes both the analog and digital processing components in a UWB system. The simulation combined with the future UWB test board will allow us to understand more about system trade-offs as a basis of future ultra wideband system design.

    A digital backend with basic synchronization and tracking functionalities will be first implemented via BEE emulation engine. With the help of FPGA testing, we could play with more sophisticated detection algorithm to improve the system performance from communication theory perspectives. One of an interesting topics would be how to approach Shannon limit using ultra wideband pulses.

    Currently, I am working on the ASIC design of our first-generation baseband while helping to develop the new design flow in BWRC. The design flow starts from Matlab down to GDSII layout. For more details, please refer to our publication area.

    Another research interest of mine is to explore the radio architecture and DSP algorithms suitable for UWB synchronizations and data recovery, including fast acquisition, channel estimation, and detection scheme, etc.