People:
Yida Duan, Prof. Elad Alon, Prof. Bernhard Boser
Conventional pipeline Analog-to-Digital converters
require high open-loop gain amplifiers operated in
feedback configurations to achieve precise inter-stage
gain. This approach is costly because these OTAs drive
not only the load capacitors, but also the sampling and
feedback capacitors. As a result, the power consumption
of the amplifier can be a feedback factor (i.e., 2-3X)
or more worse than its
open loop counterpart. Thus, the
goal of this project is to significantly reduce the
power consumption of pipeline ADCs by eliminating this
"feedback penalty".
Instead of placing an amplifier into a feedback
configuration, we propose to use "capacitor stacking" to
achieve a precise gain of 2. During the sampling phase
(Φ1), each capacitor is charged to Vin; during the
multiplying phase (Φ2), the 2 load capacitors are
stacked on top of each other so that the differential
output signal is two times Vin minus a small offset.
The main challenges in this approach are the issues
caused by the charge injection and parasitic capacitance
of the switches. Since a virtual ground is no longer
available, bottom-plate sampling technique is not an
option, and so the signal-dependent charge injected by
the switches connected to the top plate of the load
capacitors (S1 & S2) lead to distortion. Similarly,
charge sharing between the load capacitors and the
drain/source capacitance of these switches also leads to
distortion. Although these issues limit the attainable
resolution of the ADC at a given conversion rate, this
approach has the potential to achieve significant
improvements in the ADC's energy-per-conversion step.
Fig. 1: Schematic of Inter-Stage Gain Block
