People:
Hanh-Phuc Le, Prof.
Seth Sanders, Prof. Elad Alon
CMOS chips
have evolved to operate at steadily lower supply
voltages and increasing power densities, leading to
drastic reductions in the required impedance of the
supply distribution network. For example, today’s 1V,
100A microprocessors require a supply impedance of ~1mΩ,
which is extremely challenging to achieve across a broad
range of frequencies. Indeed, this impedance
requirement limits the amount of current that can be
efficiently delivered onto the die, limiting the ability
to improve performance by integrating additional cores.
Furthermore, supporting multiple independent supply
voltages on the die (for improved power management) is
currently very challenging due to the impedance
degradation associated with heavily partitioned package
power planes.
In
order to overcome these challenges, in this project we
will study, design, and fabricate fully integrated
voltage converters that maximize the overall efficiency
and robustness of high-performance digital chips. To
allow for multiple on-chip supply voltages and simplify
the board- and package-level power delivery networks, we
will focus on an architecture consisting of many
distributed, fully-integrated switching regulators (for
efficient conversion of a single external high-voltage
supply) combined with parallel linear regulators to
control the AC impedance. Since the parallel linear
regulator can be designed to spend minimal power in
setting the effective supply impedance [1], the
switching regulator can be optimized purely for
conversion efficiency.
As an additional benefit, integrating the voltage
converter onto the die relaxes the impedance
requirements of the global supply, potentially leading
to significant simplifications in the complexity of the
package and PCB power distribution networks.
Fig. 1: Example
On-Die Switching Converter and its Peak Optimal Efficiency vs. Power
Density.
