SSHAFT Manifesto

(Note: we're phasing this page out, so please use the User Guide and Reference Manual in the future)

Quick Links:

SSHAFT Setup
Chip Assembly		Function Verification		Performance Estimation
SSHAFT Design Flow Directive Reference	SSHAFT Repository		SSHAFT API		SSHAFT Technology File Reference

Introduction

This is the old homepage of the SSHAFT design flow (Simulink-to-Silicon Hierarchical Automated Flow Tool). The goal of the SSHAFT flow is ease the development of direct-mapped digital signal processing (DSP) hardware by providing a fast, automated design flow from a dataflow graph description to mask layout. The links above take you to the developing support pages for the flow. If you would like to know general information about the philosophy and goals of the flow, please follow the publication links below.

Publications

W. Rhett Davis, Ning Zhang, Kevin Camera, Fred Chen, Dejan Markovic, Nathan Chan, Borivoje Nikolic, Robert W. Brodersen, "A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems", IEEE Custom Integrated Circuits Conference, May 7-9, 2001, San Diego, CA.
- Proceedings Paper (PDF)
- Presentation Slides (Power Point)

IC Projects

	SOVA Chip
	(completed Summer '01) Lead System Designer: Engling Yeo Collaborators: Rhett Davis, Stephanie Augsburger, Tina Smilkstein The Soft-Output Viterbi Algorithm (SOVA) has been recently examined as a building block in iterative decoders for high-speed magnetic storage. These decoders promise significant bit-error performance improvement over conventional decoders at the expense of increased complexity. This chip includes inner and outer decoder building blocks for an iterative decoder and uses a novel register-exchange method for calculating survivor paths [ref]. This chip was the first to pass through our design flow with a single phase clock! [ref] E. Yeo, et al, “VLSI architectures for iterative decoders in magnetic recording channels,” IEEE Trans. on Magnetics, vol. 37, pp. 748-55, March 2001.
	Parallel Decimation Filter
	(completed Spring '00) Collaborators: Rhett Davis, Ning Zhang, Kevin Camera, Fred Chen, Paul Husted, Dejan Markovic, Hayden So, Ben Coates, Dave Wang This chip was a portion of a larger design which included the timing-recovery subsystem for the same CDMA system which inspired the CDMA Channel Estimator chip described below. Part of the system included a massively parallel decimation filter for a sigma-delta ADC used as part of the phased-locked loop. This was mainly intended to be a short-cut to implementation, but it became a great test-case for the automated design-flow. This chip was the first to pass through the "push-button" silicon assembly flow (recently named SSHAFT) in April 2000. The design was done entirely in Simulink by Paul, except for the floor-plan which was created with Cadence's Design Planner by me. The automated flow began with the generation of an EDIF file from the Simulink view by a home-grown netlisting tool developed by Hayden called BCC. The modules were developed by Ben and Dave, the flip-flops by Fred, and the clock drivers by Dejan. Kevin developed a tool called sf2vhd which translates Stateflow blocks in Simulink into synthesizable VHDL code. I was responsible for the synthesis (Design Compiler), floor-planning, place & route (QPlace and IC Craftsman), and physical verification flows (Calibre), as well as all of the automation and new technlogy files. Other verification flows were developed by Fred (logic with TimeMill), Ning (timing with PathMill), and Dejan (clock-tree with Arcadia and Spectre). The chip was designed in ST's 0.25 um technology for 1V 25 MHz operation and a power dissipation of 10 mW. It contains 300K transistors and has a die size of 3.5 x 3.0 mm.