Slides from YODA Meetings

   Fall 2005

• 11/10/05  Delay and Leakage Current Measurement Results by Liang-Teck (540K)

• 12/1/05  Collaborative Platform for DFM by Wojtek (7.1M)

   Spring 2005

• 2/18/05  Ultra Low Power SRAM Design by Huifang (1.8M)

• 2/18/05  ECC, Energy Consumption and Voltage Scaling in SRAM by Animesh (383K)

• 2/25/05  FINFET SRAM Design Progress by Zheng (3.7M)

• 4/1/05  Overview on Low Voltage Logic Styles by Louis (300K)

• 4/1/05  Stacking vs. Logic Depth for Controlling Leakage by Mircea (1M)

• 4/8/05  Energy-Delay Optimization Analysis in 90nm Design by Dejan (120K)

   Fall 2004

• 10/15/04  Ultra Dense Networks by Jan (2.6M)

• 10/22/04  Exploiting Prediction to Reduce Power on Buses by Victor (9.6M)

                           Slides on ULV circuit design brainstorming results (38K)

• 10/30/04  Power-Aware and Temperature-Aware Circuit Design by Mircea (1.4M)

• 11/5/04    Distributed Sampling of Smooth Fields using Precision Limited Sensors by Animesh (360K) 

       Pass transistor chain simulation results by Mircea (280K)

• 11/12/04  Ultra Low Voltage SRAM Design by Huifang (4.4M)

• 11/19/04  FinFET SRAM Design by Zheng (2.7M)

• 12/15/04  Delay and Power Variability Study by Ruth (155K)

"LVS technology for the Intel Pentium 4 processor on 90nm technology", D. J. Deleganes, et. al, Intel Technology Journal, vol. 8, issue 01, Feb. 18 2004.

"The fundamental limit on binary switching energy for terascale integration (TSI)", J. D. Meindl and J. A. Davis, JSSC, vol. 35, no. 10, Oct. 2000