Reliability-aware VLSI System Design Platform 

  Increased statistical process and environmental variations have led to dramatic yield loss in VLSI design for nanometer technology. In order to improve system robustness, we are developing a reliability-aware design platform that cohesively optimizes timing, power consumption, and variability of VLSI systems from the physical technology up to architecture and system level definitions. Current efforts focus on establishing a mapping methodology between circuit parametric variations ( including both process and run-time fluctuations) and performance specifications under various operation conditions.

Leakage Suppression of Embedded SRAM with Robust State Preservation

  The data retention behavior of SRAM under ultra low supply voltage (Vdd) was modeled and verified with a test chip implemented in a 0.13m technology. It was demonstrated that the state of an industrial low-leakage SRAM design can be preserved at sub-300mV standby Vdd, with over 90% leakage savings. Current research focuses on error tolerant design of SRAM ultra-low voltage standby operation.

Reliable Design of Finite State Machines Under Ultra-Low Supply Voltages

  Decreasing the power dissipation of digital integrated circuits to ultra-low levels requires the use of drastic new design approaches, such as lowering supply voltages to 500mV and below. However, operating under such low voltages introduces substantial increases in both gate delay and gate delay variability, which ultimately manifest as significant timing errors. In order to compensate for the resulting loss in reliability, the nature and sensitivity of these errors must be modeled and understood as they relate to different components of a system. Specifically, the introduction of errors into finite state machine controllers is investigated, using probabilistic state transitions to model the timing faults. The goal is to identify and compensate for error-sensitive components of the FSM using the minimal amount of redundancy and additional hardware.

Parameter Fluctuation Modeling and Testing

  Presently a CMOS testchip in 90nm technology is being designed to investigate the effects of proximity on transistor performance and leakage. For each test structure, there will be several different transistor configurations. These configurations consist of transistors with different proximity conditions. These structures will be replicated throughout the testchip. We hope to quantify the reduction in performance fluctuations due to the use of regular layout. We also hope to obtain interesting data on the effects of layout on performance spread.

Synthesis for Manufacturability

  In deep-submicron technology, yield improvement is as much a design problem as it is a manufacturing problem. Yield is defined as the percentage of manufactured products that meet all performance and functionality specifications. Parametric yield loss usually refers to the effects on circuit performance caused by process variations; functional (or catastrophic) yield loss refers to physical and structural defects that cause the circuit to fail completely. Presently, optimization for catastrophic yield is performed at a post-synthesis stage: first synthesis targets area and timing, then the design is optimized for yield at the layout level. This synthesis approach is based on the assumption that larger area leads to lower yield. However, for complex nanometer designs yield may depend more on design attributes than on total chip area. Presently, manufacturability optimization techniques performed at a post-synthesis stage have been shown capable of reducing manufacturing cost up to 10%.

  As in other cases, raising the abstraction layer where optimization is applied is expected to yield substantial gains. This work focuses on a new approach to design for manufacturability: logic synthesis for manufacturability. This methodology consists of replacing the traditional area-driven technology mapping with a new manufacturability-driven one. We have leveraged existing logic synthesis tools to test our method. The results obtained by using STMicroelectronics 0.13micron library confirm that this approach is a promising solution for designing circuits with lower manufacturing cost, while retaining performance. We have also shown that our synthesis for manufacturability can achieve even larger cost reduction when yield--optimized cells are added to the library, thus enabling a wider area-yield tradeoff exploration.