People Projects Pictures

Group Publications

Reference Papers

  • A. Wang, A. Chandrakasan, "A 180mV FFT processor using subthreshold circuit techniques," ISSCC, 2004.
  • J.W. Tschanz, S. Narendra, R. Nair, V. De, "Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors," IEEE Journal of Solid State Circuits, Vol 38, Issue 5, May 2003.
  • Y. Cao, et al, "Design sensitivities to variability: extrapolations and assessments in nanometer VLSI," IEEE ASIC/SoC, Sept. 2002.
  • J. W. Tschanz, J.T. Kao, S. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid State Circuits, Nov. 2002.
  • R. W. Brodersen, M. Horowitz, D. Markovic, B. Nikolic, V. Stojanovic, "Methods for true power minimization," ICCAD, 2002. 
  • K.A. Bowman, J.D. Meindl, "Impact of within-die parameter fluctuations on future maximum clock frequency distributions," IEEE Conference on Custom Integrated Circuits, 2001.
  • H. Soeleman, K. Roy, B.C. Paul, "Robust subthreshold logic for ultra-low power operation," IEEE Transactions on VLSI Systems, Feb. 2001.
  • S.R. Nassif, "Design for variability in DSM technologies [deep submicron technologies]," IEEE First International Symposium on Quality Electronic Design, 2000.
  • M. Eisele, J. Berthold, D. Schmitt-Landsiedel, R. Mahnkopf, "The impact of intra-die decvice parameter variations on path delays and on the design for yield of low voltage digital circuits," IEEE Transactions on VLSI Systems, Dec. 1997.
  • S. Adai, Y. Wada, "Technology challenges for integration near and below 0.1µm," Proceedings of IEEE, Apr. 1997.
  • S. Dhar, M. A. Franklin, "Optimum buffer circuits for driving long uniform lines," IEEE Journal of Solid State Circuits, Jan. 1991. 

 



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