SUE Tutorial

Version 4.1


Table of Contents

SUE Features

Getting Started

Starting Up SUE

Drawing A Schematic

Running Simulators

Higher Level Schematics

Higher Level Simulations

Cross Probing With MAX


SUE Tutorial 4.1

 
Welcome to MMI-SUE (Schematic User Environment) from Micro Magic Inc. SUE is more than just a schematic capture program. It is a complete graphical user environment.

SUE Features

This tutorial will carefully walk you through these features and many more.

Getting Started

Before we get started make sure someone has already installed SUE at your site.
INFO:   To run some parts of the tutorial you will need to have programs like HSPICE, Verilog, and IRSIM (IRSIM switch level simulator is included with MMI-SUE). If you do not have one or more of these simulators, simply skip that section and go on to the next.

Starting Up SUE

Before starting up SUE, make a new directory. Go to that new directory and type:
cp -r $MMI_TOOLS/tutorials/sue .
Don't forget the "."
cd sue
Typing "echo $MMI_TOOLS" will tell you where the MMI tools are installed. The directory you just copied contains files that you will need to run the tutorial.
Then to start SUE type:
sue
A window should come up that looks something like this:

Figure 1: SUE Window

 

SUE Screen Layout

On the very top of the window the title bar should say:
SUE: no_name S <path_to_cell> (spice)
"no_name" means that you have not specified the file (schematic) you wish to edit. The "S" means that you are editing a "Schematic", as opposed to an ICON.
Also, in parenthesis, you'll see spice displayed. This means that you are currently in spice simulation mode.

Next across the top you should see the menu bar which contains the following menu items: File, Edit, View, Sim and Help.

These are pull down menus much like any Mac, or PC application.

Directly to the right of the Help menu is the "SUE Info Bar". It currently says "Welcome to Micro Magic SUE (MMI_SUE4.1.5)". Note that the 4.1.5(or what ever the number is) refers to the version of SUE you are running.

Icon Library List Boxes

Down the right side of the window are several small Library List boxes.
The top one is the Schematic List Box. This lists all current schematics that have been loaded into SUE. Currently only no_name should be listed.

The next box is the Icon List Box. This Icon Library List box typically displays all of the Icons SUE has loaded for your current schematic. It should be blank for now.

The next two (sometimes only one) Library List Boxes are typically used to display the Icons for various library elements. These are sometimes referred to as "Lib List" boxes in this document. In this example the mspice and devices libraries are shown.

Scroll bars are shown across the bottom and right side of SUE (and are found in the List boxes). These work like the scroll bars in most other applications.

The Help Menu


 

Figure 2: Help Menu

 

Drawing A Schematic

OK, we are now ready to draw a schematic using SUE.
We are going to draw a very simple (and not very useful) circuit that simply generates a pulse. The circuit we are going to draw is:

 

Figure 3: Simple SUE Schematic

 

Creating a New File

First we will name this file.

Beginning the Schematic

Now to draw our schematic.
Be careful NOT to click the middle mouse button (Button-2) in the Library List box as it will bring up the ICON for editing.

Selecting and Editing Objects


 

Figure 4: Edit Properties pop-up for inverter

 

Generators in SUE


 

Figure 5: Edit Generator Form for nand

 

Wiring Up the Circuit

We are now ready to wire up the circuit.

 

Figure 6: Wiring by Touch

 

Running Simulators

Running HSPICE

Plotting Your SPICE Output

Now you will start to see some of the real power of SUE.

Running IRSIM On Your Schematic

Interacting with IRSIM

Netlisting And Node Names

When we plotted a node in the analyzer window, you might have noticed that a name appeared on the left side of the waveform. That is the name that SUE gave to the node when netlisting it.
You could have given it a name yourself by dropping a name_net_s, from the "devices" Lib List box, on the wire and editing its properties, but since you didn't SUE made one up. The other way a net gets assigned a name is if you have attached a port to the net (see the next section).
TIP!    Because it may be difficult to select the small name_net icon, first place a name_net_s icon in an open area in your schematic. Double click with button-1 on it and name it. Once it has been named, move it onto the desired net.
When you select a wire, SUE will show the name of that wire in the Menu Message box. In this case it will be something like "net_1". This feature is quite useful when running HSPICE.
INFO:   HSPICE only recognizes 14-character names, and allows only certain characters. SUE, on the other hand, will let you name a node almost anything you want. If you happened to name a node something that HSPICE won't accept, SUE will automatically convert that name into something HSPICE can handle.

Higher Level Schematics

Verilog

We have already simulated our little pulse generator in IRSIM and in HSPICE. Now we want to run a Verilog simulation. Unfortunately, you can't simply set nodes in Verilog like you can in IRSIM. You need to have a test file to drive them. To accomplish this we will first make an ICON for our cell, and then wire our ICON up to a clock generator that has been provided for you.

Adding Ports

Before we make our ICON we need to add some I/O ports to our circuit. We are going to place and name them as shown in Figure 7.

 

Figure 7: Adding Ports to a Schematic

 

Naming Multiple Signals


 

Figure 8: Name Selected

 

Making An ICON For Our Circuit

We are now ready to create an ICON for the Pulse_generator.

 

Figure 9: Icon View

 

Notice that SUE has placed the ports for you.

The "+" is the origin of the ICON. It is used for placement, rotation, etc. The text lines saying "-type user -name name/M/DPC" are user properties that will appear in the Edit Properties dialog box if you do an "edit properties" (double click with the left mouse button) for this cell.

Now we want to draw a representation of what we expect our Pulse_generator ICON to look like when we place it into another schematic. For this example, we will just draw a box with some text in it. We are going to make our ICON look like Figure 10.


 

Figure 10: Icon for Pulse Generator

 

Drawing the ICON

Adding Text

Let's add some text to our cell. First, we will type in the name of the cell, so we know what the cell is when placing the ICON.

Placing our ICON into the schematic

Let's see what our ICON looks like. To do this, we are going to place our ICON into our schematic.

 

Figure 11: Schematic with Icon

 

Don't worry, SUE is smart enough to know it's the ICON for this schematic and to avoid recursive calls when netlisting.

Modifying the ICON

Just in case your name isn't Bob (yes, I know there are lots of you) let's change the name in the ICON.

 

Figure 12: Schematic with Title Bar

 

And finally, let's add a title box to our schematic.

Using our Pulse_Generator


 

Figure 13: Test_pg Schematic

 

Place a copy of Pulse_generator.

You Are Now Ready to Simulate Your Circuit

Creating Behavioral Verilog Models And Attaching Them To ICONs


 

Figure 14: Verilog Property

 

Creating a More Complex Verilog Model

For the inverter in the above example, the Verilog model could be described in a single line. If you need to write a more complex Verilog model, you can attach a behavioral Verilog file to a schematic. We'll use the Pulse_generator from the above example.

 

Figure 15: Template for Verilog Model

 

Notice the SUE automatically creates a template for the behavioral model automatically adding the port information to the file. You would add the behavioral model for Pulse_generator after the line:

Higher Level Simulations

You have:
Drawn a schematic.
Simulated it in HSPICE
Simulated it in IRSIM
Simulated it in Verilog
Created ICONs, behavioral Verilog models, etc.
You see that you can do a lot with SUE.

A More Complex Example

Now let's look at something a little more complex.

 

Figure 16: Demo_ripple_4_bus Schematic

 

TIP!    You can choose the default for your docs to be in either HTML or text in your .suerc file. You can also choose your text editor and browser in your .suerc file as well. See the SUE manual for more details.
Feel free to look over the adder example. It has documentation, buses, and lots of other interesting things not covered in your simple Pulse_generator.
TIP!    SUE is smart enough to remember where you just were. Let's say you just pushed down five levels and you want to pop back up four levels. To accomplish this just repeat Ctrl-e four times. To push back down type e four times.

Displaying Design Hierarchy, And Controlling What Gets Simulated

One of the more powerful features in SUE is that it can change what you simulate on the fly. The display design hierarchy feature allows you to not only display the hierarchy, but to control what level of the design gets simulated.

To control what gets Verilog simulated, SUE uses two types of files. Those with the ".vh" extension are hierarchical Verilog files which SUE creates automatically for you. Files with a ".vb" extension are "behavioral" Verilog files, which are hand written by you.

SUE and Verilog Netlisting

When SUE builds a Verilog netlist (".vh" file) it starts from the cell you are currently in (the root cell) and looks for all of the subcells and wires connecting them together. SUE then looks at each subcell to see if there is a behavioral model for that cell (".vb").
If a ".vb" file exists (behavioral model) and if you told the netlister to use the behavioral model (via the display design hierarchy menu item) SUE will simply insert the ".vb" model for that subcell.
If no ".vb" file existed, or if you told the netlister to push down further, SUE will push down into each subcell where it does the same netlisting operation of looking at subcells and wires connecting them, while continuously building up a netlist.
If you do not tell SUE to use any behavioral models, SUE will follow down each subcell all the way to the Lib devices (i.e. nmos, pmos, inverters, etc.).

 

Figure 17: Design Hierarchy Dialog Box

 

Now let's look at an example of how you can control what you simulate using SUE.

Now look at the file Demo_ripple_4_bus.vh again. Notice it has changed. What has happened is that there was a .vb file for ripple_4_bus. The "-I" told you that SUE was going to netlist with that .vb file (associated with the ICON for that schematic).

When you clicked on the ICON line SUE expanded down a level to the FA ICONs, thus displaying -I FA. At the same time SUE generated a new Demo_ripple_4_bus.vh file.

 

Figure 18: Expanded Design Hierarchy

 

Cross Probing With MAX

If you purchased MAX (also from Micro Magic Inc.) along with SUE, you can do what is called "cross probing" between SUE and MAX. Both SUE and MAX have complete tcl/tk interfaces. This means that you can write and execute full tcl programs in either tool. Tcl also provides a means for inter-program communication. SUE and MAX use this notion of "send" commands to talk to each other. Cross-probing is one example of this inter-program communication.

 

Figure 19: FA Schematic

 


 

Figure 20: Net Selected in SUE

 


 

Figure 21: Highlighted Net in MAX

 

MAX is a very powerful, full custom layout editor with a complete language and API. Refer to the MAX Manual and MAX Tutorial (accessed from the Help menu) for more details.