Lab assignments are due at midnight of the due date. No late labs will be accepted. Submit all the relevant files electronically. Make sure there is a HTML report file named "report.htm", with links to all other files submitted. After the assignment is graded, your TA will create in the directory a file named "score.htm" reporting the score and a short comment.
The objective of this assignment is to get acquainted with the Xilinx ISE tools for VHDL logic design, timing simulation with ModelSim, and hardware design using Xilinx System Generator under Matlab Simulink. This is a very demanding lab, make sure you start as early as possible!!!
Before attempting the lab, you need to go through the following Tutorials:
Unless otherwise specified, the default setting for Xilinx software should use the following settings:
As part of this lab, we want you to keep an on-line notebook as discussed in lecture. For each problem, create a separate entry in the notebook. Be sure to follow these steps:
While you are doing this lab (and all the rest in this semester), keep your notebook. When you finish, figure out how long (to the nearest 15 minutes) you spent on each problem. A sample notebook can be found at labproject page on our class website. Submit your notebook with your report.
For this problem, using Xilinx ISE and ModelSim ONLY, write a simple
behavioral VHDL file model a 32-bit adder. For this part, you are allowed to use
the std_logic_arith functions. Verify the correct functionality of the adder
with ModelSim using the behavioral model only. Turn in the VHDL file and the
waveform showing the correct functionality. Then synthesize and implement the
adder, record down the critical path delay and total area (in number of slices).
Use floor planner to determine the architecture of the adder implemented. (i.e,
carry-save, ripple-carry, carry-look-ahead, etc.)
Hint: the VHDL file can be done with less than 10 lines.
For this problem , using Xilinx ISE and ModelSim ONLY, you are to design a 32-bit ripple-carry adder (P&H, p. 235). First write a component-level structural VHDL file for one bit slice of the adder. No functions are allowed for this part. Only logic equations are allowed. Then, write a top-level VHDL file that instantiates the bit slice as component, and structurally create the 32-bit ripple-carry adder. Then synthesize and implement the adder, record down the critical path delay and total area (in number of slices). Turn in both VHDL files and the waveform showing the correct functionality and the critical path delay. Compare the result with that in Problem 1, explain any differences or similarities.
Using Xilinx System Generator, select the AddSub block from the Xilinx\Math library, configure it to be a 32 bit integer 2's complement adder with zero latency implemented with Smart-IP core. Complete the system by adding one ramp block (start at 1, increment 1 per sample) and one constant block with value 1 as the two inputs to the adder (through appropriate input gateways), then use an output gateway to connect the output of the adder to a scope. Configure the simulation to only run for 5 cycles. Turn in the Simulink MDL files and the scope display. Then use the System Generator block to generate the ISE project files and the VHDL files. Synthesis and implement the adder, record down the critical path delay and total area (in number of slices). Now, go back to Simulink schematic, and change the adder configuration to NOT use Smart-IP core. Rerun the System Generator block, synthesis and implement the adder again, record down the the critical path delay and total area (in number of slices). Compare the two types of VHDL files you get, note any differences. Which one has better performance? Smaller area?
Design a 32-bit carry-look-ahead adder (P&H, p.246) in System Generator. (hint: the AddSub block is NOT a carry-look-ahead adder). Test out it functionality in Simulink, then synthesize and implement the adder, record down the critical path delay and total area (in number of slices). Turn in the Simulink MDL files, show post placement & routing ModelSim simulation waveform of the adder. Compare the performance and area between this implementation and the one in Problem 3 using Smart-IP core. Which one is faster? Smaller? If both flavor of adder were implemented on silicon chip rather than with FPGA, will the result be different? If so, how?