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Projects
The project forms an essential part of the EE141 experience.
Project 2: Adder Design - Due Mon Dec 5 at 11pm
The goal of this project is to design an 8-bit adder optimized for minimum delay-area product. As in the first project, work in a group of two students. No need to sign up. Full description of project 2 can be found here (Word | PDF).
You will need to prepare a 6-slide presentation and deliver a 7-minute oral presentation. You will submit the slides electronically. Also, you have to submit your pre-layout and post-layout netlists (we will run LVS on them).
Presentation template is available (PPT). Please follow directions given in the template.
Useful Resources:
· Hierarchical schematic entry in Cadence (notes from discussion/lab).
· Read the link about using hierarchy in Cadence.
· Extra LAB session for project help: the week of Nov 28 – Dec 2.
· Feel free to ask any questions!
Project 1: Clock
Distribution Network - Due Mon Oct 31 at 5pm
This project will be divided into four groups. Each group will work on
the same problem, with slightly different parameters. Please pick one set
of parameters and sign up by Tuesday Oct 18 (
The project descriptions for the four different groups are available below in MS-Word format.
·
A10:
(n1 = 2, n2 = 4, n3 = 6, Dmax = Dmin
+ 10%) (A10-doc)
·
A20:
(n1 = 2, n2 = 4, n3 = 6, Dmax = Dmin
+ 20%) (A20-doc)
·
B10:
(n1 = 3, n2 = 6, n3 = 9, Dmax = Dmin
+ 10%) (B10-doc)
·
B20:
(n1 = 3, n2 = 6, n3 = 9, Dmax = Dmin
+ 20%) (B20-doc)
Project report template (Groups A10 and B10, Groups A20 and B20).
Submission:
By preference e-mail to ee141@cory.eecs.berkeley.edu.
If not possible, provide paper copy in 240 Cory by
IMPORTANT: Before you start with any HSPICE-related work, read following Tips & Background material. This will help you get started with HSPICE verification.
More
Project 1 Tips: NEW
Here is Matlab help on fmincon function. This function effectively solves constrained optimization problems. Referring to the help document, in your case f(x) would be energy, and c(x) would be delay – target_delay. Hope this will get you going…
Although not directly applicable to your project, you may also find interesting to read early papers about buffer chain sizing. See papers by Lin-Linholm-1975, and Ma-Franzon-94.
Please do not hesitate to ask questions!
Have fun, and good luck!
Some extra information - help
- Writing input vectors in SPICE to test your adder can be tedious, here's a script that may help. NEW
- Schematics/LayoutXL Demo NEW
- Babak's Netlist Mapper NEW to convert numbered nodes to your node names.
- Using hierarchy in Cadence
- Computing logical effort
- Logical effort for different logic families