EE141: Digital Integrated Circuits
Fall 2005

Week

Date

Lecture

Due

Reading

1

Tue - Aug 30

Lec1 - Introduction

Ch-1

Thu - Sep 1

Lec2 - Design Metrics

Ch-1

2

Tue - Sept 6

Lec3 - IC Manufacturing and Design Rules

Ch-1,2

Thu - Sept 8

Lec4 - MOS Transistor Model

Hw 1

Ch-5/3

3

Tue - Sept 13

Lec5 - CMOS Inverter, VTC

Ch-5/5

Thu - Sept 15

Lec6 - MOS Capacitance & Propagation Delay

Hw 2 (sol)

Ch-5/3

4

Tue - Sept 20

Lec7 - Propagation Delay, Power Consumption

Ch-5

Thu - Sept 22

Lec8 - Buffer Sizing

Hw 3 (sol)

Ch-5

5

Tue - Sept 27

Lec9 - CMOS Scaling

Ch-5

Thu - Sept 29

Lec10 - Introduction to Wires

Hw 4 (sol)

Ch-4

6

Tue - Oct 4

Lec11 - Wire Models

Ch-4

Thu - Oct 6

Midterm 1, 6:30-8:00pm, 277 Cory (sol, stats)

7

Tue - Oct 11

Lec12 - Wires, CMOS

Ch-4,6

Thu - Oct 13

Lec13 - CMOS Logic (cont.)

Hw 5 (sol)

Ch-6

8

Tue - Oct 18

Lec14 - CMOS Logic, Logical Effort  (LE notes)

Ch-6

Thu - Oct 20

Lec15 - Logical Effort, Ratioed Logic

Hw 6 (sol)

Ch-6

9

Tue - Oct 25

Lec16 - Pass-Transistor Logic

Ch-6

Thu - Oct 27

Lec17 - Dynamic Logic

Project 1

Ch-6

10

Tue - Nov 1

Lec18 - Adders

Ch-11

Thu - Nov 3

Lec19 - Adders, Multipliers (sizing example)

Hw 7 (sol)

Ch-11

11

Tue - Nov 8

Lec20 - Shifters, Power in CMOS

Ch-6,11

Thu - Nov 10

Midterm 2, 6:30-8:00pm, 101 Morgan (sol)

12

Tue - Nov 15

Lec21 - Sequential Circuits

Ch-7

Thu - Nov 17

Lec22 - Sequential Circuits (cont.)

Hw-8 (sol)

Ch-7

13

Tue - Nov 22

Lec23 - Timing

Ch-10

Thu - Nov 24

No Lecture (Happy Thanksgiving!)

Ch-9

14

Tue - Nov 29

Lec24 - Clock Distribution, Interconnect

Hw 9 (sol)

Ch-9

Thu - Dec 1

Lec25 - Power Distribution, Memory

Ch-9,12

15

Tue - Dec 6

Project Presentations

Project 2

Thu - Dec 8

Lec26 - Memory, Perspectives

16

Thu - Dec 15

Final, 5-8pm, 105 North Gate