Spring 2003

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The project forms an essential part of the EECS141 experience.

Project 1: Clock Driver Design  - Due Th March 20 at 5pm

You are to pick one driver topology and one specific optimization goal (energy minimization, or delay penalty minimization for a given amount of slack in delay or energy reduction, respectively). Please sign up for one specific target by THURSDAY March 7 (5pm). Groups of 2 preferred.

  Follow links in the Table to see exact solutions.

("Delay" and "Energy" links summarize all results for a particular group)

(this is overall energy-delay plane for all designs, and some insights about optimal Vdd and fanout)

(all solutions are obtained based on our standard energy and delay models and fmincon function in Matlab)

The project descriptions for the four global groups (AD, AE, BD, BE) are available below in word format.

AD: Topology A - Energy Minimization
AE: Topology A - Delay Penalty Minimization
BD: Topology B - Energy Minimization
BE: Topology B - Delay Penalty Minimization

Project Report Template (Energy Minimization) (Delay Penalty Minimization)

By preference e-mail to: ee141@bwrc.eecs.berkeley.edu. If not possible, provide paper copy in 558 Cory by 5pm Th.

• It would help to keep updated with the newsgroup information in this final stage.

References

Here are links to some related papers. Don't over-analyze them, try to get main design ideas and intuition.

[1] H.Lin, L.Linholm, An Optimized Output Stage for MOS Integrated Circuits, IEEE JSSC, pp. 106-9, Apr 1975.
[2] S.Vemuru, A.Thorbjornsen, Variable-Taper CMOS Buffer, IEEE JSSC, pp. 1265-9, Sept. 1991.
[3] S.Ma, P.Franzon, Energy Control and Accurate Delay Estimation in the Design of CMOS Buffers, IEEE JSSC, pp. 1150-3, Sept. 1994.
[4] V.Stojanovic, D.Markovic, B.Nikolic, M.Horowotz, R.Brodersen, Energy-Delay Tradeoffs in Combinational Logic Using Gate Sizing and Supply Voltage Optimization, ESSCIRC, Sept. 2002.
[5] R.Brodersen, M.Horowitz, D.Markovic, B.Nikolic, V.Stojanovic, Methods for True Power Minimization, ICCAD, Nov. 2002.
 

Project 2: A REALLY FAST DIVIDER (Due Th May 8)

You are to design a divider that realizes the minimum time to divide two 8-bit numbers.

Project Description

Extra constraint (small but important): You are allowed to use AT MOST 4 adder modules (that is, N-bit adders) in your design.

Your results are to be reported in a poster session on Thu. May 8 (1:30-5pm).

Note: Please also email your project presentation slides to ee141@bwrc.eecs.berkeley.edu before Thu. May 8 5pm. This is to back up the class project material and to facilitate the project grading.

Project Poster Template and Instructions