A report is expected at both week 9 and week 15. To make the results available to the complete group and to make your results more dynamic, you will be required to provide them as web-entries. For those of you not familiar with the creation of a web-page, please refer to A Beginners Guide to HTML . Excellent web-page composers exist and most word processing and presentation tools provide a web output generator.
Paul Friedberg, Ruth Wang, "Impact of Device and Intrinsic Circuit Variability on Performance"
Mark Chew, Nathan Pletcher, "Clock Synchronization for PicoRadios "
David Fang, Dimitrios Katsis, "Circuit Design Techniques for SOI Technology"
Zhiming Deng, Jie Zhou, "Comparison of Logic Families for Low Power Sub-Threshold Designs"
Mounir Bohsali, Michael Doan, "Design of Regularly Structured Wallace Tree Multipliers"
Steven Lanzisera, Maryam Ziaei-Moayyed, "Ultra Low Power Arithmetic Circuits"
Daewon Ha, Hiu Yung Wong, "An Evaluation of the Robustness of Different Devices to Process Variations and their Impacts on the Performance of Digital Circuits"
Liang Teck Pang, "Reducing The Impact of Process Parameter Fluctuations on CMOS Digital Integrated Circuits"
Aaron Hurst, Victoria Wang, "Soft Errors in Synchronous Logic"
Manu Seth, Daniel Good, "Asynchronous Logic for Gate-Level Leakage Control"
Donald Chai, "Leakage Power Reduction Through Input Vector Control"
Sriram Balasubramanian, Jing Yang, "Circuit-Performance Implications for FINFET Scaling"
Andrew Chang, Sean Kao, "A Study and Comparison of an Output Prediction Logic Adder"
Yatish Patel, Yury Markovskiy, "Circuits for Low Power Bus Traffic Encoding"
Nan Zhou, Jianhui Zhang, "Robust design for dealing with large parameter variation under low Vdd operation"
- Ultra-low voltage design for interconnections - error behavior of 50 mV swings on wires
- Ultra-low voltage logic
- Use of self-timing to address leakage
- Analysis in the energy-delay space of regularly-structured datapaths.
- Design of regularly structured tree multipliers.
- Partitioned datapaths for DSP
- Soft error robustness of logic.
- Leakage compensation in bitlines.
- Impact of adaptive body bias and supply voltage scaling on compensating the parameter variations.