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The html creation script kind of bungled the cross-references, making this page a little tough to read. If you have Acrobat reader available, I suggest you check out this file (pdf version) instead.

Abstract

This paper describes a fully-differential anti-alias filter (AAF) and analog-to-digital converter (ADC) for baseband processing of a wideband RF signal. The AAF is a third order elliptic low-pass filter. The ADC is a 2-2 cascade sigma-delta architecture w ith a single-bit quantizer in the first stage and a 13-level quantizer in the second stage. The system converts a 2.5 MHz input signal (5 Ms/s Nyquist rate) at an oversampling ratio (OSR) of 16, and it acheives a peak SNDR of 72.3 dB.

System Specifications

The RF specifications used in this project are a combination of the specifications extracted from the Infopad-2 system, systems using the emerging UMTS standard, and system using the existing GSM standard. A simplified model of the RF channel characterist ics is shown in See . In-Band and Out-of-Band Signal Levels.. . In this model, it is assumed that there is one near-band interferer at a 1 MHz away from the signal and one far-band interferer residing at the sampling frequency. With this model, the resultant baseband performance requirements can be extracted. These calculations can be found in See D. Sobel, L. Zheng, "Baseband filter and A/D Converter for Wideband RF receiver." EECS247 midterm report. 3/98.. , and they are summarized in See Dynamic range calculations for the converter.. ; in particuar, the dynamic range requirement is 71.4 dB at a Nyquist conversion rate of 5 Ms/s.

Baseband Architecture Selection

In See D. Sobel, L. Zheng, "Baseband filter and A/D Converter for Wideband RF receiver." EECS247 midterm report. 3/98.. , it was shown that due to the presence of a strong near-band interferer, the anti-aliasing filter requirements became impractical for OSR's below 10. Thus, two possible architectures were either an oversampled switched-capacitor filter (SCF) followed by a Nyquist-rate converter, or an oversampled sigma-delta modulator (SDM) followed by a digital decimation filter. It was shown in See D. Sobel, L. Zheng, "Baseband filter and A/D Converter for Wideband RF receiver." EECS247 midterm report. 3/98.. that for OSR's in the range of above 10, the required order of the SCF was equal to or greater than the required order of a SDM for the given dynamic range requirements. Furthermore, thermal noise in a SCF is directly proportional to the number of stages , whereas thermal noise in later stages of a SDM is suppressed by its noise-shaping characteristic. Thus, power dissipation in a thermal-noise limited SCF of a given order will be higher than that in a comparable SDM. For these reasons, a SDM architecture was chosen.

Anti-Alias Filter

Anti-alias filter specifications

As will be explained in Section See SD Modulator. , the OSR selected to be 16. Given this, the AAF specifications are derived and sumarized below. f pass = 2.5 MHz , f stop = 77.5MHz; R pass < 1 dB, R stop > -76 dB; In-band Dgrd < 40 ns; V fs = 1.8 V, DR > 76 dB, and so, In-band V noise (rm s) < 57.03 mV. Detailed calculation is attached in See Anti-alias filter specifications calculation. .

Anti-alias filter architecture

Based on the specs given above, MATLAB was used to decide the filter type and order. As shown in See Filter fype and order vs. process variation and passband ripple. , we calculated the filter order needed for different types of filters corresponding to different amount passband ripple and process variation. Three conclusions can be drawn from this table:

  1. Frequency tuning is not necessary. Up to 30% bandedge shift at 0.1 dB passband ripple, a 3-rd or 4-th order meet the specs.
  2. Designing for Rp= 0.1 dB typically won't increase filter order beyond that required for Rp=1 dB.
  3. Designing for Rp= 0.1 dB, 30% bandedge shift, elliptic filter is one order than other types, which means some hardware saving and power reduction.

So a 3-rd order elliptic filter with Rp=0.1 dB was used to accomadte futher performance degradation caused by various nonidealities. Compared with butterworth and cheby2 filters, the elliptic filter has a slightly higher group delay spead, but it turns ou t with the large transition width and low order, phase nonlinearity of this 3-rd order elliptic filter still resides inside spec.

An RC structure is chosen vs. MOSFET-C and Gm-C structure is because this is a simple AAF. As will be shown in Section See Anti-alias filter circuit implementation and simulation results. , since we can tolerate the circuit sensitivity to process variation, and since the filter is low order, a ladder is not needed. It should be noted that the oversampling nature of the converter greatly alleviates the difficulty of AAF design.

Anti-alias filter circuit implementation and simulation results

A circuit diagram of the equivalent single-ended 3rd-order RC filter is shown in See : Equivalent single-ended circuit diagram for the 3-rd order elliptic anti-alias filter. . A first order stage is followed by a biquad. Pole-zero cancellation was done to reduce the opamp unity-gain bandwidth requirement. In the real differential circuit implementation, all the capacitor value halfs, and all the resistor value doubles. So, fo r the diffrential circuit implementation, Cmin= 25fF, Cmax= 3.85PF, spread=154. The negtive resistor value can be achieved by proper connection of the positive and negtive branches. All the opamp gain are set to 1000, unity-gain bandwidth is 15MHz.

First, circuit parameters with ideal opamp are calculated in matlab to achieve the ideal transfer function. In hspice, the nominal, slow and fast case with prccess variation DR/R= %, DC/C= % were checked to make sure circuit performance is within specification. Resistor and capacitor values were scaled to adjust each opamp output gain refered to input is less or equal to 1. Component values were adjusted to get the mimimum capacitor value s pead and mimimum total capacitor value while remaining within the total noise budget. After scaling, the filter with ideal opamp can achieve Rp=0.1 dB, Rstop= -81dB, Dgrd=34ns, Vnoise(rms)=56mV. All are worst-case measurement and are within specification.

Before considering opamp nonideality, effect from component mismatch is investigated by Monte-Carlo analysis in hspice. Shown in See : Monte-Carlo analysis for component mismatch. Each data point is extracted from 100 Monte-Carlo simulation runs. Simulation also includes global process variation, which is DR/R=%, DC/C=%. Both circuits of ideal opamp and of nonideal opamp with pole- zero cancellation are simulated.. , the dashed lines represent the case of ideal opamp. Up to 5% mismatch, specifications are met. Component mismatch affects passband ripple more severely than global process variationb but given 0.5% mismatch tolerance in our project, component mismatch i s not an issue at all. By contrast, group delay spread, noise are sensitive to global process variation, so worst-case check is important.

Circuit performance degradation caused by finite opamp gain, finite unity-gain bandwidth is studied too. See : Effect of finite opamp gain.. shows finite gain effect. Both passband ripple and group delay spread are not affected until gain is lower than about 1000. Stopband attenuation is not affected too much. So, 1000 is chosen as the opamp gain in our design though with gain lower than that , eg, 100, the circuit is still working within specifications.

See : Finite opamp unity-gain bandwidth limitation before and after pole-zero cancellation.. shows how the unity-gain bandwidth affect circuit behavior. On the left, the plot shows without pole-zero cancellation, giving some safety margin for component mismatch, 30MHz is the required unity-gain frequency. With pole-zero cancellation, 10MHz is th e required unity-gain frequency. On the right, it shows finite unity-gain bandwidth helps reduce passband groupdelay apread. And it is not shown here but true that finite unity-gain bandwidth helps attenuation at stopband edge too. 15 MHz is chosen as the unity-gain frequency for our design.

Overall, a 3rd-order elliptic RC filter was designed for a 3.3 mm process. Opamp gain requirement is 1000. Opamp unity-gain frequency requirement is 15MHz. Overall performance achieved is summarized below,

Rp < 0.6 dB, Rstop <-76 dB, Dgrd < 24 ns

Vnoise(rms)= 55 mV

This result also pass the Monte-Carlo check, shown in See : Monte-Carlo analysis for component mismatch. Each data point is extracted from 100 Monte-Carlo simulation runs. Simulation also includes global process variation, which is DR/R=%, DC/C=%. Both circuits of ideal opamp and of nonideal opamp with pole- zero cancellation are simulated.. . The Hspice input deck is attached.

SD Modulator

Due to the high bandwidth of the signal to be acquired, the modulator was designed to allow suitable performance at a low OSR. This design choice requires the use of high-order, multi-bit SD structures. A more complex, low-OSR structure will also tend to be a lower power solution, as the power of the modulator increases much more dramatically with increased OSR than with increased order.

 

See . shows ideal peak SQDR 1 , where L is the modulator order, Q is the number of quantization levels, and M is the OSR. See Order, Number of Quantizer bits vs. OSR for given dynamic range. lists necessary OSR's needed to meet a given peak SQDR requirement for given a order and number of quantization bits. As CDMA communications systems are robust to discrete tones (i.e. fixed pattern noise), it was deemed that the total noise power from qu antization and distortion should be about 6 dB below the thermal noise floor. Therefore, the system was designed for a peak SQDR of 78 dB.

From See Order, Number of Quantizer bits vs. OSR for given dynamic range. , we can extract the necessary modulator order and quantizer resolution to acheive our dynamic range at reasonable OSR. It was determined that a fourth-order loop with 3-4 bits in the quantizer was sufficient to acheive our design specification while prov iding enough margin for deviation from ideal calculations. In particular, See Order, Number of Quantizer bits vs. OSR for given dynamic range. does not take into account two major sources of SQDR loss in high-order structures, namely:

  1. Inter-stage gain coefficients below unity in cascaded structures.
  2. SQDR loss due to stability problems in single-loop structures.

Due to these sources of SQDR loss in high-order SD modulators, a margin of 15 dB over the ideal SQDR presented in See Order, Number of Quantizer bits vs. OSR for given dynamic range. was included in our calculations.

Single-ended vs. Differential structure

A differential switched-capacitor structure, as depicted in See : (a) Single-ended structure (b) Equivalent differential structure. (b), was chosen for circuit implementation. As shown in See Single-Ended vs. Differential Circuits. , this circuit implementation will have roughly the same power consumption and dynamic range as the single-ended structure shown in See : (a) Single-ended structure (b) Equivalent differential structure. (a). The differential structure, however, will be more robust to circuit non-idealities such as even-order harmonic distortion and power supply fluctuation. Therefore, a differential circuit structure will be used. For the sake of simplified analysis, al l analysis in the paper will be done on the equivalent single-ended structure unless otherwise noted.

Full-Delay Integrators vs. Resonators

Our design uses a cascade of full-delaying integrators with distributed feedback. Thus, our design places all the noise transfer function (NTF) zeros at DC. SD modulators can acheive more agressive noise-shaping by optimally placing the NTF zeros across t he signal band See R.W. Adams, R. Schrier, "Stability Theory for DS modulators." in Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE press, 1997.. . In order to accomplish this, switched-capacitor resonator structures with some form of local feedback must be used. True resonators require non-delaying integrators in the feed-forward path, and thus double op-amp settling. Due to the already high-speed operation of the modulator in question, this approach was avoided. Pseudo-resonators can also be constructed using full-delay integrators, yet it was found empirically that the coefficient spread (and thus capacitor spread) of such an approach was too la rge to be practical.

Single-loop vs. cascade

Our design uses a 2-2 cascade SD architecture. As is shown in See R.W. Adams, R. Schrier, "Stability Theory for DS modulators." in Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE press, 1997.. , high-order single-loop modulators with single-bit quantizers perform far below ideal SQDR predictions due to potential instability. At OSR's below 20, increasing a single-bit loop beyond second-order results in a loss in SQDR See R.W. Adams, R. Schrier, "Stability Theory for DS modulators." in Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE press, 1997.. . Hence, single-bit single-loop architectures with order above two were eliminated from consideration.

With a sufficient number of quantization levels, however, the performance of single-loop architectures is supposed to approach the ideal SQDR limit See P. Ju, K. Suyama, "Design Considerations in High-Order Multi-bit Sigma-Delta Modulators." Proceedings of the 1997 IEEE ISCAS, p 389.. . Performance degradation due to DAC non-linearity can be suppressed using dynamic-element matching techniques, as in See R. Baird, T. Fiez, "Improved DS DAC Linearity Using Data Weighted Averaging" 1995 IEEE Symposium on Circuits and Systems, p. 13.. . Attempts were made to stabilize a fourth-order, multi-bit single-loop SD modulator for this project, but no architecture could be designed that didn't overly suffer from peak SQDR loss due to instability problems.

A 2-2 cascade is attractive due its increased stability and fourth-order noise-shaping characteristic. There are two primary drawbacks to a cascaded architecture, however. First, an interstage gain coefficient of less than unity is typically needed, thus requiring a gain of greater than unity in the recombination network. This digital gain will amplify the noise, thus directly reducing SQDR. This was compensated for by adding the 15 dB design margin described above. Also, a cascade architecture is more se nsitive to component variation as the deterministic digital gain must precisely match mismatch-determined analog interstage gain. Mismatch between the analog and digital gain will result in leakage of a error term shaped only by the first stage. Therefore , a first-stage of high-order is desirable. As mentioned previously, at low OSR there is no advantage to increasing the order of a single-loop beyond 2; hence our choice of a second-order first stage. Calculations described in section See Analog/Digital Mismatch. determined that our architecture would be robust to the mismatch under the given process variation parameters.

Single-bit vs. multi-bit quantization

The first stage of the cascade has a single-bit quantizer for ease of implementation and DAC non-linearity constraints. The second stage has a 13-level quantizer and DAC (12 decision levels). As demonstrated in Section See Quantizer and DAC Non-Linearity. , the non-linearity error introduced by the quantizer is suppressed by fourth-order shaping, and the error introduced by the DAC is suppressed by second-order shaping. The errors introduced by these two non-idealities were small enough to allow the use of 13-level quantization with minimal loss in SQDR from the ideal case.

Modulator Coefficients

See : 2-2 cascade architecture. shows the single-ended equivalent structure of the 2-2 SD modulator. The coefficients were designed to allow aggressive noise-shaping over a maximal stable input range. An intial set of coefficient values were taken from the first two stages of the 2-2-2 cascade described in See A. Feldman, "High-speed, Low-power Sigma-delta Modulators for FR Baseband Channel Applications." Ph.D. Thesis, UC-Berkeley. 1997.. . Due to the addition of the 13-level quantizer in the second stage, the coefficients in the second stage were adjusted to sufficiently exercise all the levels of the ADC. This process was iterated several times to ensure maximal input stable range. See 2-2 cascade coefficients. lists final values of the coefficients. The input stable range was determined by a million-step DC input test. See : Maximum integrator output vs. DC input. shows the maximum integrator output vs. input DC level. It can be seen that all integrator outputs remain below fullscale for inputs less that 80% fullscale. Thus, the maximum input signal is set at -2 dBFS in order to prevent integrator clipping.

 

Once the coefficients are chosen, the necessary digital recombination circuitry can be determined:

 

 

 

 

 

where gd is the digital approximation of the interstage gain coefficient. For the sake of simple digital circuits, gd is constrained to be a power of two.

SD performance analysis

See : Simplified linear model of 2-2 cascade. shows a linear model of the SD with the quantizers and DAC's replaced with white noise sources. While the error introduced by these components is not white, previous analysis has shown that the white noise approximation is reasonable for analysis See R. Gray, "Quantization Noise is SD A/D Converters." in Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE press, 1997.. .

Second-stage quantization noise

Assuming perfect digital recombination, the spectrum of the output signal is given by equation See . :

 

The error term from the first quantizer is ideally cancelled, and the error term from the second quantizer undergoes fourth-order shaping and amplification by 1/gd = 4. Hence, the output noise is amplified by 12 dB above the ideal fourth-order case, and t his 12 dB is directly subtracted from ideal peak SQDR. A 13-level quantizer was chosen to make this error term -88.5 dBFS, and hence small when compared to the desired peak SQDR of 78 dB.

Analog/Digital Mismatch

As shown in equation See . , gd is a digital gain coefficient representing the product of 4 independent capacitor ratios. These four capacitor ratios comprise 7 independent capacitors (the third integrating capacitor defines both au3 and af3.) Therefore, gain mismatch, d g, should be times the capacitor mismatch, d c. ( d g = d c = 1.3%)

With a mismatch of d g, the spectrum of the output signal becomes:

 

Analog/digital mismatch prevents perfect cancellation of the first-stage error noise, and thus allows leakage of a second-order shaped error term. At 1.3% mismatch, the power of the error leakage term is -83 dBFS, and analytical calculations predict that 79 dB peak SQDR can be attained with up to 2% mismatch. This error leakage term will be the performance-limiting factor for this SD modulator at higher OSR's. Thus, with OSR >> 16, SQDR will only improve improve at roughly 15 dB/octave.

See : Peak SQDR vs. A/D gain mismatch. shows theoretical and simulated peak SQDR, modelling the two error sources shown in equation See . . Correlation between simulated points and analytical predictions is very good, suggesting that the white noise approximation is valid in this situation.

 

Finite DC Amplifier Gain

Ideal integrators have infinite gain at DC. In actual switched capacitor integrators, finite DC op-amp gain will move the integrator pole inside the unit circle, resulting in a "leaky" integrator. An expression for the new integrator transfer fu nction is:

 

 

where ai is the integrator gain as set by the capacitor ratio, Cs / Ci , and Avo is the opamp DC gain.

With this new integrator transfer function, the spectrum of the output signal can be calculated (ignoring gd mismatch):

 

where e1, e2 are the leakage terms for the first and second integrators. The leakage from the third and fourth integrators appear only in higher-shaped terms and their effects will be neglible in comparison to e1, e2 . The middle term of equation See . shows that leaky integrators will cause leakage of both unshaped and first-order shaped quantization error. The unshaped error is proportional to the product of the first two leakage factors, and will be negligible for reasonable gains. The first-order-s haped error is proportional to the sum of the first two leakage constants. Therefore, the op-amps' DC gain must be high enough to make this term negligible. From equation See . , it can be calculated that DC gains of 700 result in leakage of an error term which is -91 dBFS, and hence negligible. See : Peak SQDR vs. op-amp DC gain. shows a plot of peak SQDR vs. op-amp DC gain (with 2% a/d gain mismatch). As can be seen on this plot, DC gains above 600 results in a loss of less than 1 dB. For very low gains, simulated results are much lower than predicted results. This is because lo w DC gains also affect the numerator of the integrator's transfer function, thus exacerbating analog/digital gain mismatch.

For the purposes of our design, an amplifier gain of 700 was chosen. This should minimally affect peak SQDR performance. With the selection of an actual silicon process, however, caution should be made to make sure that the op-amp is sufficiently linear o ver its full-scale operating region. For this reason, op-amps with higher DC gain may be needed.

 

Quantizer and DAC Non-Linearity

The 13-level quantizer is a flash architecture, consisting of 12 fully differential comparators referenced to a resistor string as shown in See : (a) 13-level quantizer (b) 13-level DAC. (a). In actuality, this comparator will suffer from non-linearity errors due to resistor mismatch, op-amp offset, hysteresis, and other such phenomenon. All of these non-idealities can be represented as an additional error term added at the quantizer. Thu s this non-linearity error is shaped by fourth-order differentiation just as the quantization noise from this quantizer is shaped. Therefore, provided that the quantizer is monotonic, (i.e. its non-linearity error power is less than its quantization erro r power), the quantizer can be treated as an ideal component.

The DAC is comprised of a 13-level differential resistor string as shown in See : (a) 13-level quantizer (b) 13-level DAC. (b), similar to that in See B. Brandt, B. Wooley, "A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2-MHz A/D Covnersion. " JSSC 12/97.. . Due to resistor mismatch, the DAC will also add an error term to the signal output. As the error is added directly into the signal path at the input to the second stage, the DAC error term does not undergo any shaping in the modulator. The error term is shaped by second-order differentiation in the recombination filter; hence the output signal looks like:

 

where EDAC is the white noise approximation for the error inserted due to DAC non-linearity. For 0.5% mismatch, EDAC was calculated to be roughly -46.5 dBFS (see See White-Noise Estimate of DAC non-linearity error. for calculation of EDAC .) The second-order differentiation of EDAC suppresses its power by another 49 dB. Hence, the error term for EDAC at 0.5% component mismatch should be roughly -95.4 dBFS, a neglible term when compared to other noise sources.

Random resistor mismatches were generated, and it was found empirically that the modulator could tolerate a mismatch s of up to 1.5% without the 6 s -SQDR dropping below 80 dB (see See : Peak SQDR vs. DAC componenet mismatch (100 simulations at each mismatch point). ). Theoretical results match well with simulated results, as explained in See White-Noise Estimate of DAC non-linearity error. .

It is worth noting that the choice of a differential architecture greatly assists in suppressing non-linearities in the DAC by removing second-order harmonics. Viewed in another manner, it can be observed that the DAC output has no error at positive and n egative full-scale and at zero output. The fact that the DAC error is "pinned" to zero at three points on its transfer function limits the maximum INL deviation that the DAC can reach. Thus, a differential DAC will be inherently more linear than a single-ended DAC.

The values of the resistor strings can be calculated for appropriate settling of the ADC and DAC, and these calculations are shown in See DAC/ADC Resistor String calculation. . Due to the small capacitances used, the total resistance of the resistor strings for the DAC and ADC can be as big as 11.1 k W and 20 kW, respectively (unit R sized at 925 W , 1.6 k W ). Thus, less than 0.5 mW in total will be dissipated by these resistor strings.

Slew-rate limiting and linear settling

It has been shown that every integrator in a SD modulators does not need to settle to the full precision of the converter See L. Williams, "Modelling and Design of High-Resolution Sigma-Delta Modulators." Ph.D. Thesis, Stanford Univ. 1993.. . In particular, errors introduced by incomplete settling in integrators further down the modulator chain are shaped by the integrators preceding it when referred to the input. MIDAS simulations were used to determine necessary settling requirements. See : Settling requirements for (a) integrator 1, (b) integrator 2, (c) integrator 3, (d) integrator 4. (a)-(d) show contours of constant peak SQDR for given settling parameters in each integrator. As can be seen in these figures, the settling requirements are relaxed in integrators further down the chain.

The desired performance was 78 dB peak SQDR. Assuming a clock speed of 80 MHz, and 2.5ns overhead for clock non-overlap (i.e. 5ns of settling), the required settling performance for each integrator can determined (see See Required settling performance and total sampling capacitance for each integrator. ). Note that the first integrator has two acceptable design points: one which is slew-rate dominated and one that in settling dominated. With the selection of the actual silicon process, it would remain to be determined as to which design point results in optimal power dissipation. Some further amount of over-design will be required due to the fact that MIDAS simulations assume the opamp has only a single pole. The settling requirements are relaxed further down the SD pipeline, with the exception of the fourth integrator slewing requirement. It is inferred that this integrator needs a higher slew rate than otherwise expected in order to sufficiently exercise all DAC levels.

Thermal noise and capacitor sizing

Sampling capacitors must be sized to allow the required 71.4 dB of dynamic range. It is worth noting that the noise-shaping characteristic of SD modulators shapes the thermal noise from amplifiers further down the pipeline; thus, the dominant source of thermal noise is from the first sampling capacitor, and sampling capacitors from later integrators can be reduced in size for power optimization. The total thermal noise power of the 2-2 cascade can be expressed as: See A. Feldman, "High-speed, Low-power Sigma-delta Modulators for FR Baseband Channel Applications." Ph.D. Thesis, UC-Berkeley. 1997..

 

where g is a multiplicative factor to account for amplifier noise factor and 1/f noise. Since this is a wideband application, it was assumed 1/f noise would not be totally dominant, and a g factor of 3 was assumed. See Required settling performance and total sampling capacitance for each integrator. lists the total sampling capacitance needed for each integrator. It was assumed that a minimum-sized capacitor of 25 fF (25 m m by 25 m m metal caps at 0.4 fF/ m m2) were available. The thermal noise from the third and fourth integrator is suppressed to such a degree that its capacitor size is dictated by this process limitation (which makes the sampling capacitance larger than desired due to coefficient spread). Assuming a VFS of 1.8V and a maximum input sinusoid of -2 dBFS, peak SNDR is predicted to be 72.1 dB. A simplified, single-ended equivalent diagram of the modulator is shown in See : Simplified, single-end equivalent of modulator circuit diagram. (NOTE: All integrators are standard, two-phase full-delaying; switches are not drawn for ease of viewing.). .

Decimation Filter

A diagram of the decimation filter is shown See : Decimation Filter structure. . It consists of a order 5, length 4 decimate-by-four comb filter, followed by two decimate-by-two, length 21 low pass digital filters. This 3-stage design is neccessary to sufficiently suppress the near-band blocker; if a two-stage design were used (with a decimate-by-8 comb), the near-band blocker would alias into the signal band without sufficient supression. The filters' frequency responses are shown in See : Decimation filter Transfer Functions. , and their coefficients are included in the attached MIDAS deck.

Simulation Results

Simulink was used to verify first-order calculations for the SD modulator, and MIDAS was used to extensively simulate the modulator and its various non-idealities. Matlab was used to generate random mismatch parameters. All relevant files and flowcharts are attached.

See : SQDR vs. input amplitude. shows a MIDAS simulation of SQDR vs. input amplitude range. In this figure, all non-idealities were simulated, except thermal noise. The design point was a peak SQDR of 78 dB (i.e. quantization-and-distortion noise power 6 dB below the thermal noise floo r). Simulations verified a peak SQDR of 79.4 dB.

See : SNDR vs. input amplitude. shows a MIDAS simulation of SNDR vs. input amplitude range. In this simulation, all non-idealities discussed were included; hence the design target was 71.4 dB dynamic range. Simulations showed a DR of 72.2 dB and a peak SNDR of 72.3 dB. See : FFT of decimated MIDAS output. and See : FFT of undecimated MIDAS output. shows the FFT of the output signal (input at -2 dBFS) after and before decimation. See : FFT of undecimated MIDAS output. shows the typical noise-shaping characteristic, and one can observe in See : FFT of decimated MIDAS output. that there are no strong idle tones present.

References

  1. D. Sobel, L. Zheng, "Baseband filter and A/D Converter for Wideband RF receiver." EECS247 midterm report. 3/98.
  2. R.W. Adams, R. Schrier, "Stability Theory for DS modulators." in Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE press, 1997.
  3. P. Ju, K. Suyama, "Design Considerations in High-Order Multi-bit Sigma-Delta Modulators." Proceedings of the 1997 IEEE ISCAS, p 389.
  4. R. Baird, T. Fiez, "Improved DS DAC Linearity Using Data Weighted Averaging" 1995 IEEE Symposium on Circuits and Systems, p. 13.
  5. A. Feldman, "High-speed, Low-power Sigma-delta Modulators for FR Baseband Channel Applications." Ph.D. Thesis, UC-Berkeley. 1997.
  6. R. Gray, "Quantization Noise is SD A/D Converters." in Delta-Sigma Data Converters: Theory, Design, and Simulation. IEEE press, 1997.
  7. B. Brandt, B. Wooley, "A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2-MHz A/D Covnersion. " JSSC 12/97.
  8. L. Williams, "Modelling and Design of High-Resolution Sigma-Delta Modulators." Ph.D. Thesis, Stanford Univ. 1993.
  9. Murata SAW filter specifications sheets (from murata.com)
  10. Single-Ended vs. Differential Circuits

This appendix is used to show the power and dynamic range equivalencies between similarly structured single-ended and differential switched-capacitor circuits.

First, assume a single-ended circuit structure, as shown in See : (a) Single-ended structure (b) Equivalent differential structure. (a). Here the gain of the circuit is unity, but the following argument is applicable for non-unity gain. The peak-to-peak output swing of the amplifier (assuming common-source output stage) is:

 

Hence, the peak signal power is:

 

And the thermal noise, from equation See . is:

 

Therefore, the dynamic range for a single-ended structure can be expressed as:

 

In the case of the differential structure shown in See : (a) Single-ended structure (b) Equivalent differential structure. (b), the following equations hold:

 

The output swing is doubled, due to the differential nature of the circuit. The thermal noise is quadrupled: a factor of 2 comes from the fact that the individual capacitor sizes are halved; the other factor of two is due to the differential nature of the circuit, and hence double the number of noise sources.

When these new values are plugged back into equation See . , it is found that the single-ended and differential structures shown in See : (a) Single-ended structure (b) Equivalent differential structure. have the same dynamic range.

These two structures also have the same power consumption to first-order. This can be seen as the differential structure has twice as many current legs (due to its differential nature), but each current leg must run only half as much current due to the fa ct that it drives a half-sized capacitance.

As the two structures are similar in terms of dynamic range and power, the differential structure was chosen due to its robustness to power supply variation and even-order distortion. Equivalent single-ended structures (via the transformation described ab ove) were used in all analysis for the sake of simplicity.

  1. Anti-alias filter specifications calculation

As explained in Section 3.0, an oversampling ratio of 16 was selected. Given signal bandwidth 2.5MHz, ADC sampling frequency is 80MHz. So, AAF passband edge fp = 2.5 MHz, stopband edge fstop = fs - 2.5MHz = 77.5 MHz.

Passband ripple (1 dB) and passband group delay spread (40 ns, corresponding to 10% period @ 2.5 MHz) were chosed following typical commercial AAF examples for the similar communication systems. See Murata SAW filter specifications sheets (from murata.com).

The required carrier to noise ratio for the system is 15 dB Table 1. The far-end interferer is 69 dB stronger than the desired signal. Noting RF receiver before the AAF has 13 dB attenuation at 80 MHz from the carrier [1], given 5dB safety margin, the sto pband attenuation Rstop = 15+69-13+5 = 76 dB. And for the same argument, required DR is 76 dB.

In-band noise requirement is calculated below for DR= 76 dB for the equivalent single-ended circuit. As discussed in section See Modulator Coefficients. , maximum input signal for a stable SD modulator following the AAF is 0.8 full scale range. So, maximam AAF output V p-p is 0.8*Vfs .

 

and DR= 10*log10(P signal / P noise), for DR= 76 dB,

P noise =6.506 nV2 (from -2.5MHz to 2.5MHz), hence,

 

for frequency from 0 to 2.5MHz.

  1. White-Noise Estimate of DAC non-linearity error

This appendix is used to derive an approximation of the power of EDAC shown in See : Simplified linear model of 2-2 cascade. based on the differential resistor-string DAC (RDAC) architecture of See : (a) 13-level quantizer (b) 13-level DAC. (b).

It is important to note that a differential N-level RDAC is inherently more linear that a single-ended N-level RDAC. This characteristic can be explained as follows: assuming the digital input spans plus/minus fullscale, both DAC structures have a perfect output (i.e. no error) at plus or minus full-scale digital input. The single-ended RDAC will have its worst case error at midscale (i.e. digital zero) input. The differential output at midscale, however, will be identically zero (see See : (a) 13-level quantizer (b) 13-level DAC. (b)); hence it will have no error at midscale. This will in effect clamp the maximum error value and result is a more linear RDAC structure. Viewed another way, a differential RDAC is free from even-order non-linearity.

A differential RDAC structure has odd symmetry; hence the non-linearity of half of the structure (digital input from zero to fullscale,) can be analyzed and attributed to negative digital inputs.

In determining the total power of EDAC , it was assumed that all the levels of the DAC were exercised with equal proabability ( Pi = 1/13). This assumption was deemed valid due because the input to the second-stage was the error output of the first stage (assumed white), and the DAC would be forced by feedback to track the input.

Under these assumptions, EDAC was calculated as follows:

 

where s DAC(n) is the standard deviation of the analog error for a digital input n .

For a resistor mismatch ( sR ) of 0.5%, the power of EDAC is predicted to be roughly -46.5 dBFS. Second-order differentiation in the digital recombination filter suppresses this noise by an additional 49 dB; hence, at 0.5% component mismatch, we expect the in-band power of EDAC to be roughly -95.5 dBFS.

From See : Peak SQDR vs. DAC componenet mismatch (100 simulations at each mismatch point). , we can see that average peak SQDR drops from 86 dB to 85.5 dB with the addition of 0.5% DAC component mismatch. The 0.5 dB drop corresponds to an additional noise term (DAC noise) that is 9 dB below the pre-existing noise term (second-stage quantization noise). Hence, simulations show that the expected power of the DAC noise is -86 dBFS - 9 dB, or -95 dBFS. As demonstrated in the previous paragraph, calculations predict the DAC noise power to be -95.5 dBFS.

  1. DAC/ADC Resistor String calculation

A simplified model of the DAC is shown in See a: Simplified DAC settling model. a. Here RT is the total value of the resistor string, Rsw is the switch resistance, and the 200 fF capacitor is the total feedback capacitance seen (from the third and fourth integrator). Cgd and Cdb will be on the order of a few fF for reasonably small t ransistors, and hence will be ignored in this analysis. (In otherwords, signal coupling via overlap capacitance from the clock signal will be negligible.)

Therefore, the settling time constant for the DAC will be roughly:

 

A conservative design choice is to allow the DAC to settle to the full resolution of the converter plus some safety margin (i.e. 80 dB). This implies roughly 9.2 t 's of settling are required in 5 ns ( t = 555 ps). Using the parameters from the 0.35 m m process given, choosing the W/L of the switch to be 10 (3.5 m m / 0.35 m m) will allow sufficient settling if RT/4 is less than 2.78 k W . This implies a total string resistance of 11.1k W or a unit resistance of 925 W .

A simplified model of a single comparator of the ADC is shown in See b: Simplified comparator model. b. Here signal coupling from the output back to the reference input must be considered. In this case, the switching of a comparator output will capacitively feedthrough to the voltage reference node; if this feedthrough effect is not sufficiently settled out, the quantizer may produce an error at its output. Again, allowing for 80 dB of settling in 5ns, a similar calculation can be made. Note that this is a very conservative design choice, as the quantizer error will be shaped by fourth-order differentiat ion. Due to the very small capacitances of the comparator input (roughly 20 fF for a 1.75 m m by 0.35 m m transistor), the ADC string will settle easily with a string resistance as large at 20 k W .

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1. In this paper, SQDR refers to signal-to-quantization-and-distortion ratio, and it accounts for all non-idealities except thermal noise.