BWRC Publications

Citation
Jing Yang, Thura Naing, Bob Brodersen. "A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS". CICC, 2009.

Abstract
An asynchronous 6bit 1GS/s ADC is achieved by time interleaving two ADCs based on binary successive approximation algorithm (SA) using a capacitive ladder. The semi-close loop asynchronous technique eliminates the high internal clocks and significantly speeds up the SA algorithm. One bit redundancy is implemented to compensate the process variation of parasitic and the MOM capacitance. Fabricated in 65nm CMOS with an active area of 0.11mm2, it achieves a peak SNDR of 31.5dB at 1 GS/s sampling rate and has a powe

Electronic downloads

• CICC_final.pdf · application/pdf · 1665 kbytes

Citation formats

• HTML

  Jing Yang, Thura Naing, Bob Brodersen. <a
  href="http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php/1102.html">A
  1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS</a>, CICC, 2009.

• Plain text

  Jing Yang, Thura Naing, Bob Brodersen. "A 1-GS/s 6-bit
  6.7-mW ADC in 65-nm CMOS". CICC, 2009.

• BibTeX

  @inproceedings{YangNaingBrodersen2009,
      author = {Jing Yang and Thura Naing and Bob Brodersen},
      title = {A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS},
      booktitle = {CICC},
      year = {2009},
      URL = {http:///php/pubs/pubs.php/1102.html}
  }
  

Posted by Jing Yang on Jul 20, 2009..

Notice: This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright.