BWRC Publications

Citation
Adam Megacz. "A 13Ghz Loadable Counter with 20ps/bit Settling Time and Early Completion, in 40nm CMOS". BWRC, October, 2, 2009.

Abstract
This talk will describe a clockless ("asynchronous") loadable counter whose cycle time is constant regardless of the number of bits in the counter. In order to achieve this constant bound, the counter keeps the internal value in a redundant representation. A settling delay is required after loading to convert the input to this representation. A layout for the counter in TSMC's 40nm GP technology is complete and DRC-clean (Calibre). Each counter bit is 810 lambda tall and bits can be packed at a 486 lambda pitch, not including well contacts. In simulations from netlists extracted from this layout (Star-RCXT, HSim) the counter exhibits a cycle time of 76ps and a worst-case settling time of 20ps/bit. This talk describes joint work with Ivan Sutherland and Jo Ebergen, using on an algorithm first proposed by Joep Kessels.

Electronic downloads

• 13ghz.counter-bwrc.pdf · application/pdf · 3669 kbytes

Citation formats

• HTML

  Adam Megacz. <a
  href="http://bwrc.eecs.berkeley.edu/php/pubs/pubs.php/1144.html"><i>A
  13Ghz Loadable Counter with 20ps/bit Settling Time and Early
  Completion, in 40nm CMOS</i></a>, BWRC, October,
  2, 2009.

• Plain text

  Adam Megacz. "A 13Ghz Loadable Counter with 20ps/bit
  Settling Time and Early Completion, in 40nm CMOS". BWRC,
  October, 2, 2009.

• BibTeX

  @seminar{Megacz2009,
      author = {Adam Megacz},
      title = {A 13Ghz Loadable Counter with 20ps/bit Settling
                Time and Early Completion, in 40nm CMOS},
      organization = {BWRC},
      month = {October},
      day = {2},
      year = {2009},
      URL = {http:///php/pubs/pubs.php/1144.html}
  }
  

Posted by Olivia Nolan on Oct 6, 2009..

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