Digital Circuit and Board Design for a

Low Power, Wideband CDMA Receiver

Ian David O'Donnell, M.S. 1996  (advisor: Robert Brodersen)

This thesis covers digital design issues relating to custom and semi-custom integrated circuit and printed circuit board design associated with the high-speed, digital backend to the InfoPad’s Spread-Spectrum, Direct-Sequence CDMA radio [Sheng91], [Sheng96]. The goal of this radio system is to support up to 50 users per picocell at a rate of 2 Mb/s each which requires a sampling rate of 128 MHz for the digital receiver. The digital baseband circuitry implements timing and data recovery, hand-off, and channel estimation for a battery powered, hand-held mobile unit. Hence, low power consumption was a primary issue in the design. A low power, low cost custom digital ASIC was designed and fabricated to provide a subset of this functionality in 57mm 2 in a ‘pseudo’ 0.8u CMOS process, dissipating 19mW in half-speed operation. Coarse and fine lock, raw data recovery (no DQPSK decoding), and some channel correlation estimation are currently implemented and have been tested. A redesign is also underway to complete the desired functionality, including DQPSK decoding, adjacent cell scan, and multi-path channel and data correlation estimation. This thesis describes the design process and documents the testboard and important integrated circuit structures in the backend chip. Together with [Stone95], which covers the control circuitry and an overview of the desired functionality, the complete digital backend chip is described.