Analysis and Circuit Design for Low Power Programmable Logic Nodules

Eric A. Kusse, M.S.1998 (advisor: Jan Rabaey).

This thesis presents research in low power programmable logic. In particular, programmable gate array (PGA) structures are examined emphasizing their strengths and weaknesses from a power perspective. A detailed analysis of power consumption for a Xilinx XC4003A was conducted to gain insights into what blocks of a PGA consume the most power and how those elements contribute to a mapped design’s total power. In addition, several circuit design issues pertaining to PGAs were studied. Several problems sur-rounding low voltage pass transistor design were identified and solutions were evaluated. Based on the results from the power analysis and the circuit studies, a new PGA architecture has been defined. Finally, a 2x4 mini-array implementation of the design in a 3-layer metal, 0.6um CMOS process has been completed. Extracted simulations show order of magnitude energy improvements over the 4003A with only a factor of 2 speed penalty using a dual supply voltage of 1.5 and 2 volts.