A 2-GHz Low-Power Single-Chip CMOS Receiver for WCDMA Applications

Dennis Yee, Chinh Doan, David Sobel, Brian Limketkai, Saf Alalusi, Robert Brodersen, 

ESCARP 2000 Stockholm, Sweden

This paper describes a 2-GHz single-chip 0.25 mm CMOS receiver for WCDMA applications. The receiver is based on a direct-conversion architecture and implements all RF components, including the  low-noise amplifier, frequency synthesizer, and mixers.  The receiver also integrates all base band components along the in-phase and quadrature signal paths, each of which includes a first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s åD analog-to-digital converter operating at 200 MHz.  The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW.