Design and Implemenatation of a 2-GHz Low-Power CMOS Receiver for WCDMA Applications

Dennis Yee, David Sobel, Chinh Doan, Brian Limketkai, Johan Vanderhaegen, and Robert Brodersen. Workshop on New Trends in RF CMOS Transceivers (University of Pavia - June 20-21, 2000).

This paper describes the design and implementation of a 2-GHz single-chip 0.25-mm CMOS receiver for a custom WCDMA system.  A system-level simulation framework is used to explore the trade-offs between analog front-end impairments and system performance.  System specifications are chosen in order to facilitate a low-power highly-integrated implementation.  The receiver is based on a direct-conversion architecture and implements all RF components, including the low-noise amplifier, frequency synthesizer, and mixers.  The first-order high-pass filter, a second-order Sallen and Key low-pass filter, and a 7-bit 25-MS/s  SD analog-to-digital converter operating at 200MHz.  The receiver prototype achieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mW.