Evaluation and Guidence in Processor Architecture Selection for DSP

Naji Sami Ghazal,  Ph.D 2000 (advisor: Jan Rabaey).

With today’s rapidly growing use of signal processing, communication, and multi-media applications in electronic systems, programmable Digital Signal Processors (DSPs) have recently emerged into the mainstream of embedded systems design with architectures growing in diversification and innovation. The choices faced by a designer have multiplied: from enhanced conventional DSPs, to new RISC-like DSPs, to general-purpose processors and micro-controllers with added DSP support. As a result it has become increasingly difficult for designers to determine the appropriate architecture for the intended applications and design constraints. Unfortunately, due to the irregularity of DSP architecture, even for a single DSP processor, it has been difficult to reach or predict optimal implementation of a given application from a behavioral description. Even the latest software development tools have been unable to extract the true potential of a DSP processor in implementing an application, without requiring the designer’s in-depth knowledge of the architecture. In this research work, a novel approach is taken to address today’s growing need for automated guidance in architecture selection and design development of DSP systems. This dissertation presents a new technique for early estimation of DSP software by using encapsulation of knowledge about the DSP application domain and DSP architectural features. This method, called Retargetable Estimation, produces aggressive predictions of the likely bottlenecks and potential optimization opportunities to guide the designer toward the development of the applications’ optimal implementation on a particular processor architecture. This technique is made quickly retargetable to a wide range of different architectures by using a parameterized architecture model that emphasizes the salient optimizing features of a DSP architecture. Experimental results presented in this work show that Retargetable Estimation can be used to predict expert hand-optimized performance of DSP-oriented applications reliably, exceeding the reach of DSP compilers by two orders of magnitude. A method is also proposed to determine the expected confidence level of this scheme’s estimation results. Furthermore, as the intent of this research is to provide guidance for design with focus on varying design metrics, a demonstration of applying this retargetable performance estimation scheme to another increasingly important metric, power consumption, is provided in this dissertation.