Project Overview

This project seeks to achieve ultra-low power high-performance multimedia computing through the reconfiguration of heterogeneous system modules. Achieving high-energy efficiency requires the elimination of the waste that typically dominates the energy consumption in general-purpose programmable engines. Providing programmability at just the right granularity (instruction, functional module, data path or gate) makes it possible to eliminate virtually all overhead, while making it further possible to exploit other energy reducing techniques, such as parallellism, pipelining and dynamic voltage scaling.

To achieve this goal, the project introduces and integrates a number of novel approaches and techniques:

• Combines multiple computational granularity levels on the same die
• "On-the-fly" processor composition leads to orders of magnitude in power reduction.
• Template for "domain-specific" processors
• Data-driven synchronization
• General-purpose embedded processors with a power-scalable performance.
• On-chip integrated and efficient dc-dc converters.
• Low power embedded PGA's and reconfigurable data paths
• Globally asynchronous, locally synchronous design, low-swing interconnect, adaptive voltage and clock frequency scaling
• Quantifyable design methodology supports design-space exploration

Research Sub-Areas